Integrated Components Which Have Both Horizontally-Oriented Transistors and Vertically-Oriented Transistors
US-2024306399-A1 · Sep 12, 2024 · US
US9941263B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9941263-B2 |
| Application number | US-201615052521-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 24, 2016 |
| Priority date | Aug 28, 2013 |
| Publication date | Apr 10, 2018 |
| Grant date | Apr 10, 2018 |
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Disclosed herein is a semiconductor integrated circuit device which includes a standard cell with a plurality of fins extending in a first direction and arranged in a second direction that is perpendicular to the first direction. An active fin of the fins forms part of an active transistor. A dummy fin of the fins is disposed between the active fin and an end of the standard cell.
Opening claim text (preview).
What is claimed is: 1. A semiconductor integrated circuit device comprising: a first cell row comprised of standard cells arranged in a first direction; and a second cell row comprised of standard cells arranged in the first direction, and disposed adjacent to the first cell row in a second direction that is perpendicular to the first direction, wherein the first cell row comprises: a first standard cell having fins extending in the first direction and including an active transistor with a fin structure, the active transistor having at least one of the fins and a gate line extending in the second direction; and a second standard cell which is a TAP cell having a function of fixing a substrate potential, the second standard cell being adjacent to the first standard cell in the first direction, and including fins extending in the first direction, and the first standard cell has a first fin disposed closest to a cell row boundary between the first and second cell rows, and the second standard cell has a dummy fin disposed at the same position in the second direction as the first fin and a diffusion region supplied with power and disposed at a position farther from the cell row boundary than the dummy fin in the second direction. 2. The semiconductor integrated circuit device of claim 1 , wherein the second standard cell has a power supply line disposed at the cell row boundary and supplying the diffusion region with power.
Layouts of interconnections · CPC title
comprising FinFETs · CPC title
comprising FinFETs · CPC title
Electricity · mapped topic
Electricity · mapped topic
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