Integrated millimeter-wave chip package

Patent metadata

Field	Value
Publication number	US-9941226-B2
Application number	US-201414569791-A
Country	US
Kind code	B2
Filing date	Dec 15, 2014
Priority date	Dec 15, 2014
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

An integrated millimeter-wave chip package structure including an interposer structure, a millimeter-wave chip and a substrate is provided. The interposer structure includes at least an antenna pattern and at least a plated through-hole structure penetrating through the interposer structure and connected to the at least one antenna pattern. The millimeter-wave chip is electrically connected to the at least antenna pattern located either above or below the millimeter-wave chip through the at least plated through-hole structure.

First claim

What is claimed is:

1. An integrated millimeter-wave chip package structure, comprising:
a first interposer structure, wherein the first interposer structure comprises a first metal layer, a second metal layer and an insulating support layer located between the first and second metal layers, and the first interposer structure includes at least one first plated through-hole structure, penetrating through the first metal layer, the insulating support layer and the second metal layer and electrically connecting the first metal layer and second metal layer;
at least one chip, coupled to the first interposer structure, wherein the at least one chip has an active surface and contact pads located in the active surface of the at least one chip; and
a first substrate, coupled to the first interposer structure, wherein the first substrate comprises at least one insulating layer and a third metal layer located on the at last one insulating layer, wherein the third metal layer is located on one side of the first substrate facing the first interposer structure, the first metal layer of the first interposer structure comprises at least one antenna pattern, the at least one antenna pattern is located above or below the at least one chip, the at least one chip is electrically connected to the at least one antenna pattern through the at least one first plated through-hole structure of the first interposer structure,
wherein a portion of the at least one chip protrudes toward the first interposer structure from a surface of the first substrate facing the first interposer structure, and the active surface of the at least one chip is located between the surface of the first substrate and the first interposer structure.

2. The package structure of claim 1 , wherein the first substrate has a concave cavity, the at least one chip is buried inside the concave cavity and the active surface of the at least one chip faces the second metal layer of the first interposer structure, the at least one chip is physically connected to the first interposer structure through bumps located between the contact pads and the second metal layer, and the at least one chip is electrically connected to the at least one antenna pattern through the bumps and the at least one first plated through-hole structure.

3. The package structure of claim 1 , wherein the first substrate has an opening exposing the at least one chip, the active surface of the at least one chip faces the second metal layer of the first interposer structure, the at least one chip is physically connected to the first interposer structure through bumps located between the contact pads and the second metal layer, and the at least one chip is electrically connected to the at least one antenna pattern through the bumps and the at least one first plated through-hole structure.

4. The package structure of claim 2 , wherein the first substrate comprises a fourth metal layer and a second plated through-hole structure, the fourth metal layer is located on an opposite side of the at least one insulating layer relative to the third metal layer, and the second plated through-hole structure penetrates through the first substrate to connect the third metal layer and the fourth metal layer located on two opposite sides of the at least one insulating layer.

5. The package structure of claim 3 , wherein the first substrate comprises a fourth metal layer and the second plated through-hole structure, the fourth metal layer is located on an opposite side of the at least one insulating layer relative to the third metal layer, and the second plated through-hole structure penetrates through the first substrate to connect the third metal layer and the fourth metal layer located on two opposite sides of the at least one insulating layer.

6. The package structure of claim 4 , further comprising a second substrate connected to the first substrate, the second substrate includes solder balls disposed between the first and second substrates, and the second substrate is physically and electrically connected to the first substrate through the solder balls.

7. The package structure of claim 5 , further comprising a second substrate connected to the first substrate, the second substrate includes solder balls disposed between the first and second substrates, and the second substrate is physically and electrically connected to the first substrate through the solder balls.

8. The package structure of claim 2 , further comprising a second interposer structure and bumps between the first interposer structure and the second interposer structure and between the first substrate and the second interposer structure, the second interposer structure includes at least one third plated through-hole structure penetrating through the second interposer structure, the second interposer structure is located between the at least one chip and the first interposer structure, and the at least one chip is connected to the second interposer structure through the bumps between the first substrate and the second interposer structure, the second interposer structure is connected to the first interposer structure through the bumps between the first interposer structure and the second interposer structure, and through the bumps between the first interposer structure and the second interposer structure and between the first substrate and the second interposer structure and the first and third plated through-hole structures, the at least one chip and the first and second interposer structures are physically and electrically connected.

9. The package structure of claim 3 , further comprising a second interposer structure and bumps, the second interposer structure includes at least one third plated through-hole structure penetrating through the second interposer structure, the second interposer structure is located between the at least one chip and the first interposer structure, and the at least one chip is connected to the second interposer structure through the bumps, the second interposer structure is connected to the first interposer structure through the bumps, and through the first and third plated through-hole structures and the bumps, the at least one chip and the first and second interposer structures are physically and electrically connected.

10. The package structure of claim 8 , wherein the first substrate comprises a fourth metal layer and a second plated through-hole structure, the fourth metal layer is located on an opposite side of the at least one insulating layer relative to the third metal layer, and the second plated through-hole structure penetrates through the first substrate to connect the third metal layer and the fourth metal layer located on two opposite sides of the at least one insulating layer.

11. The package structure of claim 9 , wherein the first substrate comprises a fourth metal layer and the second plated through-hole structure, the fourth metal layer is located on an opposite side of the at least one insulating layer relative to the third metal layer, and the second plated through-hole structure penetrates through the first substrate to connect the third metal layer and the fourth metal layer located on two opposite sides of the at least one insulating layer.

12. The package structure of claim 10 , further comprising a second substrate connected to the first substrate, the second substrate includes solder balls disposed between the first and second substrates, and the second substrate is physically and electrically connected to the first substrate through the solder balls.

13. The package structure of claim 11 , further comprising a second substrate connected to the first substrate, th

Assignees

• Ind Tech Res Inst

Inventors

• Tsai Cheng-Hua
• Chung Shyh-Jong
• Lee Ching-Kuan

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W70/681

  comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title