Integrated circuit and process for fabricating thereof

Patent metadata

Field	Value
Publication number	US-9941158-B2
Application number	US-201113211062-A
Country	US
Kind code	B2
Filing date	Aug 16, 2011
Priority date	Oct 24, 2007
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material.

First claim

What is claimed is:

1. A substrate comprising at least one dielectric layer into which a plurality of longitudinal trenches are embedded, wherein:
each of the plurality of longitudinal trenches includes a peripheral surface;
a layer of a catalytic material disposed on the peripheral surface of at least one of the plurality of longitudinal trenches, wherein the catalytic material comprises Palladium (Pd) compounds;
a layer consisting of tin disposed on the layer of catalytic material;
a first layer of a second conductive material disposed on the layer of tin;
a second layer of the second conductive material disposed on the first layer of the second conductive material to at least partially fill the at least one longitudinal trench and form a conductive path;
wherein a reduction potential of the layer of tin is less than a reduction potential of the second conductive material; and
wherein one of the plurality of longitudinal trenches extends along an entire thickness of the at least one dielectric layer in a cross-section to form a via and at least one other of the plurality of longitudinal trenches does not extend along the entire thickness of the at least one dielectric layer in the cross-section to form a trace.

2. The substrate of claim 1 , wherein the second conductive material comprises Copper (Cu).

3. A substrate comprising:
at least one dielectric layer;
a plurality of longitudinal trenches embedded in the at least one dielectric layer, each of the plurality of longitudinal trenches including a respective peripheral surface and further including:
a layer of a catalytic material disposed on the peripheral surface, wherein the catalytic material comprises Palladium (Pd) compounds;
a layer of consisting of tin disposed on the layer of catalytic material;
a first layer of a second conductive material disposed on the layer of tin;
a second layer of the second conductive material disposed on the first layer of the second conductive material to at least partially fill a respective longitudinal trench of the plurality of longitudinal trenches and form a conductive path;
wherein a reduction potential of the layer of tin is less than a reduction potential of the second conductive material; and
wherein one of the plurality of longitudinal trenches extends along an entire thickness of the at least one dielectric layer in a cross-section to form a via and at least one other of the plurality of longitudinal trenches does not extend along the entire thickness of the at least one dielectric layer in the cross-section to form a trace.

4. The substrate of claim 3 , wherein the second conductive material comprises copper.

5. A substrate comprising at least one dielectric layer into which a plurality of longitudinal trenches are embedded, wherein:
each of the plurality of longitudinal trenches includes a peripheral surface;
a single layer of a catalytic material disposed on the peripheral surface of at least one of the plurality of trenches, wherein the catalytic material comprises Palladium (Pd) compounds;
a layer consisting of tin disposed on the layer of catalytic material;
a first layer of a second conductive material disposed on the layer of tin;
a second layer of the second conductive material disposed on the first layer of the second conductive material to at least partially fill the at least one longitudinal trench and form a conductive path;
wherein a reduction potential of the layer of tin is less than a reduction potential of the second conductive material; and
wherein one of the plurality of longitudinal trenches extends along an entire thickness of the at least one dielectric layer in a cross-section to form a via and at least one other of the plurality of longitudinal trenches does not extend along the entire thickness of the at least one dielectric layer in the cross-section to form a trace.

6. The substrate of claim 5 , wherein the second conductive material comprises Copper (Cu).

7. The substrate of claim 1 , wherein the first layer of the second conductive material is disposed on the layer of tin by an electroless plating process.

8. The substrate of claim 1 , wherein the second conductive material displaces a portion of the layer of tin.

9. The substrate of claim 3 , wherein the second conductive material displaces a portion of the layer of tin.

10. The substrate of claim 5 , wherein the second conductive material displaces a portion of the layer of tin.

Assignees

• Gurumurthy Charan
• Salama Islam
• Jomaa Houssam
• Tanikella Ravi
• Intel Corp

Inventors

• Gurumurthy Charan
• Salama Islam
• Jomaa Houssam
• Tanikella Ravi

Classifications

• H10P14/46

  using a liquid · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/035

  combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers · CPC title

• H10W20/033

  in openings in dielectrics · CPC title