Concurrent access to cache dirty bits

Patent metadata

Field	Value
Publication number	US-9940247-B2
Application number	US-201213533253-A
Country	US
Kind code	B2
Filing date	Jun 26, 2012
Priority date	Jun 26, 2012
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

The present application describes embodiments of a method and apparatus for concurrently accessing dirty bits in a cache. One embodiment of the apparatus includes a cache configurable to store a plurality of lines. The lines are grouped into a plurality of subsets the plurality of lines. This embodiment of the apparatus also includes a plurality of dirty bits associated with the plurality of lines and first circuitry configurable to concurrently access the plurality of dirty bits associated with at least one of the plurality of subsets of lines.

First claim

What is claimed:

1. An apparatus, comprising:
a cache configurable to store a plurality of lines, wherein the lines are grouped into a plurality of subsets of the plurality of lines;
a plurality of dirty bits associated with the plurality of lines;
first circuitry configurable to concurrently access the plurality of dirty bits associated with at least one of the subsets of the plurality of lines;
a register that stores values concurrently accessed from the plurality of dirty bits; and
microcode configurable to access the register and identify dirty cache lines based on a logical combination of the values stored in register; wherein the microcode is further configurable to clean or rinse the cache by writing dirty cache lines back to memory.

2. The apparatus of claim 1 , wherein the subsets are associated with a corresponding plurality of indices of the cache, and wherein the lines in the subsets correspond to ways of the cache.

3. The apparatus of claim 2 , wherein said first circuitry is configurable to concurrently access the dirty bits associated with ways of at least one index of the cache.

4. The apparatus of claim 3 , wherein said first circuitry is configurable for parallel access to the dirty bits associated with the ways of said at least one index.

5. The apparatus of claim 1 , comprising a plurality of flip-flops to be concurrently accessed for storing the plurality of dirty bits.

6. The apparatus of claim 1 , further comprising logic to combine the concurrently accessed plurality of dirty bits to determine a status of the subset of lines.

7. The apparatus of claim 1 , further comprising circuitry to select one of the plurality of lines to probe based on a logical combination of the accessed plurality of dirty bits.

8. An apparatus, comprising:
means for storing a plurality of lines, wherein the lines are grouped into a plurality of subsets of the plurality of lines;
means for storing values of a plurality of dirty bits associated with the plurality of lines;
means for concurrently accessing the plurality of dirty bits associated with at least one of the plurality of subsets of the plurality of lines;
a register for storing values concurrently accessed from the plurality of dirty bits, and
microcode configurable to access the register and identify dirty cache lines based on a logical combination of the values stored in register, wherein the microcode is further configurable to clean or rinse the cache by writing dirty cache lines back to memory.

9. A method, comprising:
storing a plurality of lines in a cache, wherein the lines are grouped into a plurality of subsets of the plurality of lines;
storing values of a plurality of dirty bits associated with the plurality of lines; and
concurrently accessing the values of the plurality of dirty bits associated with at least one of the plurality of subsets of the plurality of lines
storing values of the dirty bits read into a register;
accessing the values of the dirty bits stored in said at least one register and identifying dirty cache lines based upon a logical combination of the values stored in the register; and
cleaning or rinsing the cache by writing dirty cache lines back to memory.

10. The method of claim 9 , wherein the subsets are associated with a corresponding plurality of indices of the cache, and wherein the lines in the subsets correspond to ways of the cache, and wherein concurrently accessing the values of the dirty bits comprises concurrently accessing values of the dirty bits associated with ways of at least one index of the cache.

11. The method of claim 10 , wherein concurrently accessing the values of the dirty bits comprises accessing, in parallel, the dirty bits associated with the ways of said at least one index.

12. The method of claim 9 , further comprising logically combining the accessed values to determine a status of the at least one of the plurality of subsets of the plurality of lines.

13. The method of claim 9 , further comprising further comprising selecting one of the plurality of lines to probe based on a logical combination of the accessed plurality of dirty bits.

14. A non-transitory computer-readable storage medium including instructions that when executed can configure a manufacturing process used to manufacture a semiconductor device comprising:
a cache configurable to store a plurality of lines, wherein the lines are grouped into a plurality of subsets of the plurality of lines;
a plurality of dirty bits associated with the plurality of lines; and
first circuitry configurable to concurrently access the plurality of dirty bits associated with at least one of the subsets of the plurality of lines;
a register that stores values concurrently accessed from the plurality of dirty bits; and
microcode configurable to access the register and identify dirty cache lines based on a logical combination of the values stored in register wherein the microcode is further configurable to clean or rinse the cache by writing dirty cache lines back to memory.

Assignees

• Walker William L
• Advanced Micro Devices Inc

Inventors

• Walker William L

Classifications

• G06F12/0893 Primary

  Caches characterised by their organisation or structure · CPC title

• G06F12/0891

  using clearing, invalidating or resetting means · CPC title

• G06F12/0815

  Cache consistency protocols · CPC title