Method and system for valid memory module configuration and verification

Patent metadata

Field	Value
Publication number	US-9940235-B2
Application number	US-201615197471-A
Country	US
Kind code	B2
Filing date	Jun 29, 2016
Priority date	Jun 29, 2016
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

Aspects of the present disclosure involve a system and method for verifying and validating accurate memory module placement on a printed circuit board. In one embodiment, the printed circuit board is configured to include actuating elements that can be used to verify correct memory module location placement on the printed circuit board. In another embodiment, the actuating elements can be used to validate accurate memory module placement. The actuating elements can be in the form of buttons that may be depressed and configured to trigger light emitting diodes (LEDs) that correspond to the slots on the printed circuit board.

First claim

What is claimed is:

1. An apparatus comprising:
a first memory slot supported on a printed circuit board, the first memory slot configured to receive a first memory module;
a second memory slot supported on the printed circuit board, the second memory slot configured to receive a second memory module;
a third memory slot supported on the printed circuit board, the third memory slot configured to receive a third memory module;
a first indicating element supported on the printed circuit board proximate the first memory slot;
a second indicating element supported on the printed circuit board proximate the second memory slot;
a third indicating element supported on the printed circuit board proximate the third memory slot; and
at least one actuating element in electrical communication with the first indicating element, the second indicating element, and the third indicating element, actuation of the at least one actuating element causing activation of the first indicating element in association with a first memory configuration where the first memory module is in the first memory slot or causing the activation of the second indicating element and the third indicating element in association with a second memory configuration providing more computer memory than the first memory configuration, and where the second memory module is in the second memory slot and the third memory module is in the third memory slot.

2. The apparatus of claim 1 , wherein the at least one actuating element is hardwired to the first indicating element, the second indicating element, and the third indicating element.

3. The apparatus of claim 1 , wherein the actuation of the at least one actuating element causes the activation of the first indicating element based on a report generated by a device driver.

4. The apparatus of claim 1 , wherein the actuation of the at least one actuating element causes that activation of the first indicating element, the second indicating element, and the third indicating element in association with the second memory configuration.

5. The apparatus of claim 1 , wherein the first memory configuration is a minimum memory configuration.

6. The apparatus of claim 1 , wherein the second memory configuration is a medium memory configuration.

7. The apparatus of claim 1 , wherein an activated indicating element causes illumination of the corresponding proximate memory slot.

8. The apparatus of claim 1 , wherein a first actuation of a first actuating element corresponds to the activation of the first indication element associated with the first memory configuration and wherein a first actuation of a second actuating element corresponds to the activation of the second indicating element and the third indicating element in association with the second memory configuration.

9. The apparatus of claim 1 , wherein a first actuation of the at least one actuating element corresponds to the activation of the first indication element associated with the first memory configuration and a second actuation of the at least one actuating element corresponds to the activation of the second indicating element and the third indicating element in association with the second memory configuration.

10. An apparatus comprising:
a plurality of memory slots coupled to a printed circuit board, the plurality of memory slots configured to receive a first plurality of memory modules associated with a first memory configuration and configured to receive a second plurality of memory modules associated with a second memory configuration;
a plurality of indicating elements, each indicating element of the plurality of indicating elements positioned adjacent to one of the plurality of memory slots; and
a first actuating element electrically connected to the plurality of indicating elements, a depression of the first actuating element illuminating a first set of the plurality of indicating elements corresponding to the first memory configuration and visually indicating into which of the plurality of memory slots the memory modules are placed to achieve the first memory configuration or illuminating a second set of the plurality of indicating elements different from the first set of the plurality of indicating elements, the second set of the plurality of indicating elements corresponding to the second memory configuration and visually indicating into which of the plurality of memory slots the memory modules are placed to achieved the second memory configuration.

11. The apparatus of claim 10 , wherein a first depression of the first actuating element illuminates the first set of the plurality of indicating elements corresponding to the first memory configuration.

12. The apparatus of claim 10 , wherein a second depression of the first actuating element illuminates the second set of the plurality of indicating elements corresponding to the second memory configuration.

13. The apparatus of claim 10 , wherein a first depression of a second actuating element illuminates the second set of the plurality of indicating elements corresponding to the second memory configuration.

14. The apparatus of claim 10 , wherein the first memory configuration is a minimum memory configuration.

15. The apparatus of claim 10 , wherein the second memory configuration is a medium memory configuration.

16. The apparatus of claim 10 , wherein the first actuating element is hardwired to the plurality of indicating elements.

17. The apparatus of claim 10 , wherein the first set of the plurality of indicating elements includes a portion of the plurality of indicating elements.

18. The apparatus of claim 12 , wherein the first and the second depressions of the first actuating element are functions of a routine that locates the corresponding first set and second set of the plurality of indicating elements to illuminate.

19. A method for determining memory slot locations for memory module placement comprising:
receiving a first input at a first actuating element electrically connected to a plurality of indicating elements; and
illuminating a first set of the plurality of indicating elements corresponding to a first memory configuration in response to the first input received at the first actuating element, wherein the illuminated first set of plurality of indicating elements visually indicate into which of a plurality of memory slots memory modules are placed to achieve the first memory configuration or illuminating a second set of the plurality of indicating elements different from the first set of the plurality of indicating elements, the second set of the plurality of indicating elements corresponding to a second memory configuration and visually indicating into which of the plurality of memory slots the memory modules are placed to achieve the second memory configuration.

20. The method of claim 19 , wherein the first actuating element is hardwired to the plurality of indicating elements.

Assignees

• Oracle Int Corp

Inventors

• Bucaro Edward Alfonso

Classifications

• G06F13/4068 Primary

  Electrical coupling · CPC title

• G06F12/0684 Primary

  with feedback, e.g. presence or absence of unit detected by addressing, overflow detection · CPC title

• G06F2212/2532

  comprising a plurality of modules · CPC title