Updating device code through a bus

Patent metadata

Field	Value
Publication number	US-9940123-B1
Application number	US-201514983459-A
Country	US
Kind code	B1
Filing date	Dec 29, 2015
Priority date	Dec 29, 2015
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

Techniques for updating code of a device may be described. In an example, bus may connect the device to a management entity. The device may run a first version of the code. A second version of the code may be available from memory. The device may access the second version from the memory, stop running the first version of the code, and start running the second version of the code without restarting the management entity or the device.

First claim

What is claimed is:

1. A system for providing firmware updates to computer components, the system comprising:
a host with a host memory storing computer-readable instructions;
a device with a device memory storing other computer-readable instructions, the device configured to run a current version of firmware from a first buffer of the device memory; and
a bus that connects the host and the device,
wherein the host, based on executing the computer-readable instructions, performs steps of:
copying an updated version of the firmware to a reserved block of the host memory, the reserved block of the host memory having a host memory address,
adding update information about the updated version of the firmware to the reserved block of the host memory, and
signaling, over the bus, the device that the updated version of the firmware is available;
wherein the device, based on executing the other computer-readable instructions, performs other steps of:
accessing a reserved block of the device memory based on the signaling, the reserved block of the device memory having a device memory address, the device memory address mapped to the host memory address based on a map associated with the bus, the reserved block of the device memory storing the updated version of the firmware and the update information based on the map, the reserved block of the device memory accessed based on a translation between the host memory address and the device memory address according to the map,
copying the updated version of the firmware to a second buffer of the device memory from the reserved block of the device memory, and
without a restart of the host or the device:
stopping running the current version of the firmware from the first buffer,
starting running the updated version of the firmware from the second buffer by at least using a sub-routine of the updated version and using a running state of the current version from a current block of the device memory, and based on the running of the updated version of the firmware:
updating the running state in the current block of the device memory,
adding variable values to another block of the device memory, and
signaling, over the bus, the host that the updated version of the firmware is running.

2. The system of claim 1 , wherein the bus is a peripheral component interconnect express (PCIe) bus, wherein the current block storing the running state does not change between stopping running the current version of the firmware and starting running the updated version of the firmware.

3. The system of claim 1 , wherein copying the updated version of the firmware to the second buffer comprises:
copying a first portion of the updated version of the firmware to the second buffer;
detecting an interrupt;
handling the interrupt; and
copying a second portion of the updated version of the firmware to the second buffer after the interrupt is handled, and
wherein a size of the first portion or the second portion of the updated version of the firmware is based on a balance between a functionality of the device and speed of update of the firmware.

4. The system of claim 1 , wherein the reserved block of the host comprises a live update buffer configured to store the updated version of the firmware and a live update control configured to store the update information, and wherein signaling the device that the updated version of the firmware is available comprises:
sending, to the device over the bus, a read transaction or a write transaction associated with a predefined location of the device memory.

5. The system of claim 1 , wherein the current version of the firmware causes the device to copy the updated version of the firmware to the second buffer, wherein the sub-routine is copied to a predefined location of the second buffer, and wherein starting the running of the updated version of the firmware comprises running the sub-routine from the predefined location to further initialize at least one of a hardware setting or register an interrupt.

6. A device, comprising:
a processing entity; and
a non-transitory computer-readable memory storing computer-readable instructions,
wherein the device, based on executing the computer-readable instructions with the processing entity, performs steps of:
communicating with a management entity over a bus;
executing a first version of code, the first version stored in a first memory block of the device;
receiving, over the bus, a request from the management entity to update the first version of the code to a second version of the code;
accessing, based on the request, a second memory block that stores the second version of the code, the second memory block mapped to a reserved memory block of the management entity based on a map associated with the bus, the second memory block accessed based on an address translation between the second memory block and the reserved memory block of the management entity, the address translation based on the map;
reading the second version of the code from the second memory block; and
without a restart of the management entity or the device:
stopping running the first version of the code from the first memory block,
starting running the second version of the code by at least using a sub-routine of the second version and using state data of the first version from a third memory block of the device, and
based on the running of the second version:
updating the state data in the third memory block,
adding variable values to a fourth memory block of the device, and
signaling, over the bus, the management entity that the second version of the firmware is running.

7. The device of claim 6 , wherein the management entity or a network location comprises the second memory block.

8. The device of claim 6 , wherein the memory of the device comprises the second memory block, wherein the first version of the code comprises a subset of the instructions, wherein the subset when executed with the processing entity causes the device to determine that the second version is available from the second memory block.

9. The device of claim 6 , wherein start running the second version of the code from the memory of the device comprises: copying the second version of the code from the second memory block to a fifth memory block of the device; and utilizing the second version from the fifth memory block to execute the code.

10. The device of claim 9 , wherein executing the first version results in state data in the third memory block of the device, wherein the state data is not copied to complete the update to the second version of the code.

11. The device of claim 6 , wherein starting running the second version of the code from the memory of the device comprises: executing the second version of the code from the second memory block: and allocating the first memory block to receiving a next version of the code.

12. The device of claim 6 , wherein the instructions when executed with the processing entity further cause the device to: identify, to a computing resource based on the request, that the device is in an updating state and that the first version of the code is stored in the first memory block, wherein the updating state and the first version of the code are identified in the second memory block, and wherein the computing resource comprises the management entity, the device, or a resource that triggered the update; and identify, to the computing resource, a completion of the update of the first version of the code to the second version of the code, wherein the completion is identified in the second memory block.

13. The device of claim 6 , wherein the instructions wh

Assignees

• Amazon Tech Inc

Inventors

• Ayoub Hani
• Bshara Nafea
• Wilson Matthew Shawn
• Sbisa Clint Joseph
• Wasserstrom Barak
• Barrett Brian William
• Shitrit Ronen
• Liguori Anthony Nicholas

Classifications

• G06F8/65 Primary

  Updates (security arrangements therefor G06F21/57) · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F8/656 Primary

  while running · CPC title

• G06F8/654

  using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories · CPC title

• G06F13/4295

  using an embedded synchronisation · CPC title