System and method for controlling various aspects of PCIe direct attached nonvolatile memory storage subsystems

Patent metadata

Field	Value
Publication number	US-9940036-B2
Application number	US-201414493560-A
Country	US
Kind code	B2
Filing date	Sep 23, 2014
Priority date	Sep 23, 2014
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

Techniques for controlling PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method including monitoring a temperature of a memory attached via the PCIe interface, determining whether an operation implemented on the attached memory has caused the temperature of the memory to exceed a preset threshold, and controlling an I/O rate of the attached memory based on the determination such that the I/O rate is greater than zero.

First claim

What is claimed is:

1. A method, comprising:
assigning a total number of system credits available for implementing operations on a memory attached via a Peripheral Component Interconnect Express (PCIe) interface, wherein the total number of system credits is based on a number of die in the attached memory and types of the operations implemented on the attached memory;
monitoring a temperature of the attached memory;
determining whether the monitored temperature of the attached memory has exceeded a preset threshold;
controlling an I/O rate of the attached memory based on the determination, wherein the I/O rate is greater than zero, and wherein the I/O rate is controlled by adjusting the total number of system credits;
assigning a credit to a new operation based on a type of the new operation and a number of die in the attached memory needed for the new operation;
comparing the assigned credit to the adjusted total number of system credits; and
releasing the new operation for execution based on the comparison of the assigned credit to the adjusted total number of system credits.

2. The method of claim 1 , wherein the attached memory is a directly attached non-volatile memory storage system.

3. The method of claim 2 , wherein the non-volatile memory storage system is a solid state drive.

4. The method of claim 3 , wherein the solid state drive is flash memory comprising stacks of die.

5. The method of claim 4 , wherein the preset threshold is a predetermined temperature.

6. The method of claim 1 , further comprising:
generating an alert based on the monitored temperature of the attached memory.

7. The method of claim 6 , wherein the alert is displayed on a user interface.

8. The method of claim 1 , wherein the I/O rate of the attached memory is decreased when it is determined that the temperature of the attached memory has exceeded the predetermined threshold.

9. The method of claim 8 , further comprising:
monitoring the temperature of the memory attached via the PCIe interface after the I/O rate has been decreased to determine whether the temperature of the memory no longer exceeds the preset threshold.

10. The method of claim 9 , wherein the I/O rate is increased when it is determined that the temperature of the memory no longer exceeds the preset threshold.

11. The method of claim 1 , further comprising:
determining whether the temperature of the attached memory has exceeded the predetermined threshold for a predetermined time period.

12. The method of claim 11 , wherein the I/O rate of the attached memory is decreased when it is determined that the temperature of the attached memory has exceeded the predetermined threshold for the predetermined time period.

13. The method of claim 11 , wherein the I/O rate of the attached memory is maintained when it is determined that the monitored temperature of the attached memory has not exceeded the predetermined threshold for the predetermined time period.

14. The method of claim 1 , further comprising:
monitoring an overall temperature of a plurality of memory attached via the PCIe interface;
determining whether the overall temperature of the plurality of the memory exceeds the preset threshold; and
controlling an overall I/O rate of the plurality of attached memory based on the determination.

15. The method of claim 1 , wherein the temperature is monitored by at least one temperature sensor.

16. The method of claim 1 , further comprising:
applying a timing offset to a plurality of operations to be implemented on the attached memory.

17. The method of claim 16 , wherein the timing offset is randomized.

18. The method of claim 16 , wherein the timing offset is static.

19. A computer program product comprised of a series of instructions executable on a computer, the computer program product implementing the steps of:
assigning a total number of system credits for implementing operations on a memory attached via a Peripheral Component Interconnect Express (PCIe) interface, wherein the total number of system credits is based on a number of die in the attached memory and types of the operations implemented on the attached memory;
monitoring a temperature of the attached memory;
determining whether the monitored temperature of the attached memory has exceeded a preset threshold;
controlling an I/O rate of the attached memory based on the determination, wherein the I/O rate is greater than zero, and wherein the I/O rate is controlled by adjusting the total number of system credits;
assigning a credit to a new operation based on a type of the new operation and a number of die in the attached memory needed for the new operation;
comparing the assigned credit to the adjusted total number of system credits; and
releasing the new operation for execution based on the comparison of the assigned credit to the adjusted total number of system credits.

20. A system comprising:
a credit management module that assigns a total number of system credits available for implementing operations on a memory attached via a Peripheral Component Interconnect Express (PCIe) interface, wherein the total number of system credits is based on a number of die in the attached memory and types of the operations implemented on the attached memory, and assigns a credit to a new operation based on a type of the new operation and a number of die in the attached memory needed for the new operation;
a temperature module that monitors a temperature of the attached memory;
a determination module that determines whether the monitored temperature of exceeded a preset threshold;
an I/O controlling unit that controls an I/O rate of the attached memory based on the determination, wherein the I/O rate is greater than zero, and wherein the I/O rate is controlled by adjusting the total number of system credits,
wherein the assigned credit is compared to the adjusted total number of system credits, and the new operation is released for execution based on the comparison of the assigned credit to the adjusted total number of system credits.

Assignees

• HGST Netherlands BV
• Western Digital Tech Inc

Inventors

• Skandakumaran Krishanth
• Medapati Arun Kumar
• Namala Sri Rama
• Narasimha Ashwin
• Kumar B Ajith

Classifications

• Y02B60/1235

  Cross-Sectional Technologies · mapped topic

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title