Peeling method and light-emitting device

Patent metadata

Field	Value
Publication number	US-9937698-B2
Application number	US-201414532634-A
Country	US
Kind code	B2
Filing date	Nov 4, 2014
Priority date	Nov 6, 2013
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

The yield of a peeling process is improved. A first step of forming a peeling layer to a thickness of greater than or equal to 0.1 nm and less than 10 nm over a substrate; a second step of forming, on the peeling layer, a layer to be peeled including a first layer in contact with the peeling layer; a third step of separating parts of the peeling layer and parts of the first layer to form a peeling trigger; and a fourth step of separating the peeling layer and the layer to be peeled are performed. The use of the thin peeling layer can improve the yield of a peeling process regardless of the structure of the layer to be peeled.

First claim

What is claimed is:

1. A peeling method comprising:
a first step of forming a peeling layer to a thickness of greater than or equal to 0.1 nm and less than 10 nm over a first substrate;
a second step of forming a layer to be peeled that is in contact with the peeling layer and includes a first layer;
a third step of attaching the layer to be peeled to a second substrate with a first bonding layer,
a fourth step of removing at least a part of the peeling layer and a part of the first layer to form a peeling trigger between the first bonding layer and the first substrate; and
a fifth step of separating the peeling layer and the layer to be peeled from the peeling trigger.

2. The peeling method according to claim 1 , wherein at least a stack comprising the first layer having stress with a negative value is formed as the layer to be peeled in the second step.

3. The peeling method according to claim 2 , wherein at least the first layer having stress with a negative value and a second layer having stress with a negative value over the first layer are formed as the stack in the second step.

4. The peeling method according to claim 3 ,
wherein the first layer comprises an oxide insulating film, and
wherein the second layer comprises a nitride insulating film.

5. The peeling method according to claim 2 , wherein at least the first layer having stress with a negative value, a second layer having stress with a negative value over the first layer, a third layer having stress with a negative value over the second layer, a fourth layer having stress with a positive value over the third layer, and a fifth layer having stress with a negative value over the fourth layer are formed as the stack in the second step.

6. The peeling method according to claim 1 , wherein N 2 O plasma treatment is not performed between the first step and the fourth step.

7. The peeling method according to claim 1 , wherein the peeling layer comprises tungsten.

8. The peeling method according to claim 1 , further comprising the step of:
curing the first bonding layer.

9. The peeling method according to claim 1 , further comprising the steps of:
forming a second bonding layer surrounding the first bonding layer, and
curing the first bonding layer and the second bonding layer,
wherein the first bonding layer, the second bonding layer, the peeling layer, and the layer to be peeled overlap one another.

10. A method for fabricating a semiconductor device, the method comprising:
a first step of forming a peeling layer to a thickness of greater than or equal to 0.1 nm and less than 10 nm over a first substrate;
a second step of forming a layer to be peeled that is in contact with the peeling layer and includes a first layer;
a third step of attaching the layer to be peeled to a second substrate with a first bonding layer,
a fourth step of removing at least a part of the peeling layer and a part of the first layer to form a peeling trigger between the first bonding layer and the first substrate; and
a fifth step of separating the peeling layer and the layer to be peeled from the peeling trigger,
wherein the layer to be peeled comprises a transistor.

11. The method according to claim 10 , wherein at least a stack comprising the first layer having stress with a negative value is formed as the layer to be peeled in the second step.

12. The method according to claim 11 , wherein at least the first layer having stress with a negative value and a second layer having stress with a negative value over the first layer are formed as the stack in the second step.

13. The method according to claim 12 ,
wherein the first layer comprises an oxide insulating film, and
wherein the second layer comprises a nitride insulating film.

14. The method according to claim 11 , wherein at least the first layer having stress with a negative value, a second layer having stress with a negative value over the first layer, a third layer having stress with a negative value over the second layer, a fourth layer having stress with a positive value over the third layer, and a fifth layer having stress with a negative value over the fourth layer are formed as the stack in the second step.

15. The method according to claim 10 , wherein N 2 O plasma treatment is not performed between the first step and the fourth step.

16. The method according to claim 10 , wherein the peeling layer comprises tungsten.

17. The method according to claim 10 , further comprising the step of:
curing the first bonding layer.

18. The method according to claim 10 , further comprising the steps of:
forming a second bonding layer surrounding the first bonding layer, and
curing the first bonding layer and the second bonding layer,
wherein the first bonding layer, the second bonding layer, the peeling layer, and the layer to be peeled overlap one another.

Assignees

• Semiconductor Energy Lab

Inventors

• Yasumoto Seiji
• Sato Masataka
• Aoyama Tomoya
• Komatsu Ryu

Classifications

• H10P72/7616

  characterised by a coating, a hardness or a material · CPC title

• H10P72/7442

  Separation by peeling · CPC title

• B32B2457/00

  Electrical equipment · CPC title

• Y10T156/1967

  Cutting delaminating means · CPC title

• Y10T156/1142

  Changing dimension during delaminating [e.g., crushing, expanding, warping, etc.] · CPC title