Multi-stacked electronic device with defect-free solder connection

US9936576B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9936576-B2
Application numberUS-201615174208-A
CountryUS
Kind codeB2
Filing dateJun 6, 2016
Priority dateJul 16, 2014
Publication dateApr 3, 2018
Grant dateApr 3, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method includes forming a multi-stacked electronic device having two or more electronic components, each of the electronic components includes a leadframe, the leadframes of each electronic component are physically joined together using a non-solder metal joining process to form a joint, and the joint is located outside a solder connection region.

First claim

Opening claim text (preview).

What is claim is: 1. A method comprising: forming a stacked electronic device having first, second and third electronic components, the first electronic component is positioned above the second and third electronic components in said stack, said second electronic component is positioned beneath the first and third electronic components in said stack, and the third electronic component is positioned between the first and second components in said stack, and the first electronic component including a lateral, outside downwardly extending first leadframe, the second electronic component including a lateral, upwardly extending second leadframe, the second leadframe extending upwardly, laterally inside of, and vertically overlapping with, the first leadframe, wherein the first and second leadframes include respective vertically overlapping portions, and the first leadframe including a lower portion spaced from said overlapping portions and defining a solder connection region for soldering the stacked electronic device to a soldering surface, the forming a stacked electronic device including using a first joining process to form a joint directly between and physically joining together the overlapping portions of the first and second leadframes, with the third electronic component positioned between the first and second electronic components, and wherein the joint is located outside the solder connection region. 2. The method according to claim 1 , wherein the forming a stacked electronic device further includes using a second joining process to join the third electronic component to one of the first and second electronic components. 3. The method according to claim 2 , wherein the using a second joining process to join the third electronic component to one of the first and second electronic components includes using the second joining process to join the third electronic component to the first electronic component. 4. The method according to claim 2 , wherein the third electronic component includes a lateral third leadframe, and the using a second joining process to join the third electronic component to one of the first and second electronic components includes using the second joining process to join the third leadframe to one of the first and second electronic components. 5. The method according to claim 4 , wherein the using the second joining process to join the third leadframe to one of the first and second electronic components includes using the second joining process to join the third leadframe to the first electronic component. 6. The method according to claim 5 , wherein the third leadframe extends upwards, laterally inside of the first leadframe. 7. The method according to claim 6 , wherein the first and third leadframes include respective vertically overlapping portions. 8. The method according to claim 7 , wherein the using the second joining process to join the third leadframe to the first electronic component includes using the second joining process to form another joint directly between and physically joining together the overlapping portions of the first and third leadframes. 9. The method according to claim 1 , wherein the non-solder metal joining process comprises brazing or welding the first and second leadframes together. 10. The method of claim 1 , wherein: the solder connection region comprises a predefined solderable area; and the soldering surface comprises a circuit board, a PCB, laminate substrate, or other electronic device. 11. A method comprising: providing a first electronic component, the first electronic component comprising a lateral, outside, downwardly extending, first leadframe; providing a second electronic component, the second electronic component comprising a lateral, upwardly extending second leadframe; providing a third electronic component; placing the third electronic component above and in close proximity with the second electronic component, and placing the first electronic component above and in close proximity with the third electronic component to form a stacked electronic device, wherein the second leadframe extends upwardly, laterally inside of, and vertically overlapping with, the first leadframe, wherein the first and second leadframes include vertically overlapping portions in a contact region, and the first leadframe includes a lower portion spaced from said overlapping portions and defining a solder connection region for soldering the stacked electronic device to a soldering surface; joining the first leadframe of the first electronic component to the second leadframe of the second electronic component using a non-solder metal joining process to form a joint in the contact region directly between and physically joining together the overlapping portions of the first and second leadframes, with the third electronic component between the first and second electronic components, and wherein the joint is located outside the solder connection region; and forming a solder connection in the solder connection region, wherein the solder connection attaches the multi-stacked electronic device to the soldering surface. 12. The method according to claim 11 , further comprising joining the third electronic component to one of the first and second electronic components using another non-solder metal joining process to form a further joint joining together the third electronic component and said one of the first and second electronic components. 13. The method according to claim 12 , wherein the using another non-solder metal joining process to form a further joint joining together the third electronic component and said one of the first and second electronic components includes using the another non-solder metal joining process to join the third electronic component to the first electronic component. 14. The method according to claim 12 , wherein the third electronic component includes a lateral third leadframe, and the using another non-solder metal joining process to join the third electronic component to one of the first and second electronic components includes using the another non-solder metal joining process to join the third leadframe to one of the first and second electronic components. 15. The method according to claim 14 , wherein the using another non-solder metal joining process to join the third leadframe to one of the first and second electronic components includes using the another non-solder metal joining process to join the third leadframe to the first electronic component.

Assignees

Inventors

Classifications

  • Encapsulations, e.g. protective coatings · CPC title

  • Leadframes · CPC title

  • Multiple chips on leadframes · CPC title

  • Package configurations · CPC title

  • of multiple leadframes in a single chip · CPC title

Patent family

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External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9936576B2 cover?
A method includes forming a multi-stacked electronic device having two or more electronic components, each of the electronic components includes a leadframe, the leadframes of each electronic component are physically joined together using a non-solder metal joining process to form a joint, and the joint is located outside a solder connection region.
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10W70/429. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 03 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).