Tamper-respondent assemblies

Patent metadata

Field	Value
Publication number	US-9936573-B2
Application number	US-201514941887-A
Country	US
Kind code	B2
Filing date	Nov 16, 2015
Priority date	Sep 25, 2015
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

Methods of fabricating tamper-respondent assemblies are provided which include a tamper-respondent electronic circuit structure. The tamper-respondent electronic circuit structure includes a tamper-respondent sensor. The tamper-respondent sensor includes, for instance, at least one flexible layer having opposite first and second sides, and circuit lines forming at least one resistive network. The circuit lines are disposed on at least one of the first or second side of the at least one flexible layer, and have a line width W l ≤200 μm, as well as a line-to-line spacing width W s ≤200 μm. In certain enhanced embodiments, the tamper-respondent sensor includes multiple flexible layers, with a first flexible layer having first circuit lines, and a second flexible layer having second circuit lines, where the first and second circuit lines may have different line widths, different line-to-line spacings, and/or be formed of different materials.

First claim

What is claimed is:

1. A fabrication method comprising:
fabricating a tamper-respondent assembly, the fabricating comprising:
providing a tamper-respondent electronic circuit structure, the providing comprising providing a tamper-respondent sensor, the providing the tamper-respondent sensor comprising:
providing multiple flexible layers disposed in a stack, at least one flexible layer of the multiple flexible layers having opposite first and second main surfaces;
providing circuit lines forming at least one resistive network, the circuit lines being disposed on at least one of the first main surface or the second main surface of the at least one flexible layer, and the circuit lines having a line width W l ≤200 μm, and a line-to-line spacing width W s ≤200 μm; and
providing another flexible layer of the multiple flexible layers of the tamper-respondent sensor, the another flexible layer being a malleable metal film layer which generates metal debris with an attempted intrusion therethrough.

2. The fabrication method of claim 1 , wherein the circuit lines have line width W l ≤100 μm, and line-to-line spacing width W s ≤100 μm.

3. The fabrication method of claim 1 , wherein the circuit lines include resistive circuit lines comprising a material, line width W l , and a line length L l which provide at least 1000 ohms resistance between ends per resistive circuit line.

4. The fabrication method of claim 3 , wherein the material comprises at least one of conductive ink, copper, silver, silver carbon or nickel-phosphorus.

5. The fabrication method of claim 1 , wherein the at least one flexible layer comprises at least one crystalline polymer layer having the opposite first and second main surfaces with the circuit lines forming the at least one resistive network disposed thereon.

6. The fabrication method of claim 5 , wherein the at least one crystalline polymer layer comprises at least one of polyvinylidene difluoride (PVDF), or polyimide.

7. The fabrication method of claim 1 , wherein the malleable metal film comprises copper or a copper alloy.

8. The fabrication method of claim 1 , wherein the tamper-respondent sensor comprises multiple flexible layers disposed in a stack, the at least one flexible layer being at least one flexible layer of the multiple flexible layers, and wherein the multiple flexible layers comprise a first flexible layer having first circuit lines, of the circuit lines, and a second flexible layer having second circuit lines, of the circuit lines, the first circuit lines having a first line width ≤200 μm and the second circuit lines having a second line width ≤200 μm, wherein the first line width of the first circuit lines is different from the second line width of the second circuit lines.

9. The fabrication method of claim 1 , further comprising providing an electronic enclosure to enclose, at least in part, at least one electronic component to be protected, the electronic enclosure comprising an outer surface, and wherein the tamper-respondent electronic circuit structure covers, at least in part, the outer surface of the electronic enclosure.

10. The fabrication method of claim 1 , further comprising providing an electronic enclosure to enclose, at least in part, at least one electronic component to be protected, the electronic enclosure comprising an inner surface, and wherein the tamper-respondent sensor overlies, at least in part, the inner surface of the electronic enclosure.

11. The fabrication method of claim 10 , further comprising:
providing a multilayer circuit board, the at least one electronic component being associated with the multilayer circuit board;
providing an embedded tamper-respondent sensor disposed within the multilayer circuit board; and
providing an electronic enclosure to seal to the multilayer circuit board, and the tamper-respondent sensor covering, at least in part, the inner surface of the electronic enclosure, and the embedded tamper-respondent sensor within the multilayer circuit board facilitate defining a secure volume about the at least one electronic component.

12. A fabrication method comprising:
fabricating a tamper-respondent assembly, the fabricating comprising:
providing a tamper-respondent electronic circuit structure, the providing comprising providing a tamper-respondent sensor, the providing the tamper-respondent sensor comprising:
providing at least one flexible layer having opposite first and second main surfaces;
providing circuit lines forming at least one resistive network, the circuit lines being disposed on at least one of the first main surface or the second main surface of the at least one flexible layer, and the circuit lines having a line width W l ≤200 μm, and a line-to-line spacing width W s ≤200 μm;

wherein the tamper-respondent sensor comprises:
multiple flexible layers disposed in a stack, the at least one flexible layer being at least one flexible layer of the multiple flexible layers, and wherein the multiple flexible layers comprise a first flexible layer having first circuit lines, of the circuit lines, and a second flexible layer having second circuit lines, of the circuit lines, the first circuit lines having a first line width ≤200 μm and the second circuit lines having a second line width ≤200 wherein the first line width of the first circuit lines is different from the second line width of the second circuit lines; and
wherein the first circuit lines are formed of a first material and the second circuit lines are formed of a second material, the first material of the first circuit lines being a different material from the second material of the second circuit lines.

13. A fabrication method comprising:
fabricating a tamper-respondent assembly, the fabricating comprising:
providing a tamper-respondent electronic circuit structure, the providing comprising providing a tamper-respondent sensor, the providing the tamper-respondent sensor comprising:
providing at least one flexible layer having opposite first and second main surfaces;
providing circuit lines forming at least one resistive network, the circuit lines being disposed on at least one of the first main surface or the second main surface of the at least one flexible layer, and the circuit lines having a line width W l ≤200 μm, and a line-to-line spacing width W s ≤200 μm;
wherein the tamper-respondent sensor further comprises multiple flexible layers disposed in a stack, the at least one flexible layer being at least one flexible layer of the multiple flexible layers, and wherein the multiple flexible layers further comprise a first flexible layer having first circuit lines, of the circuit lines, and a second flexible layer having second circuit lines, of the circuit lines, the first circuit lines being formed of a first material and the second circuit lines being formed of a second material, the first material of the first circuit lines being a different material from the second material of the second circuit lines.

Assignees

• IBM

Inventors

• Brodsky William L
• Busby James A
• Isaacs Phillip Duane
• Long David C

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W42/20

  protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title

• H10W42/405

  using active circuits · CPC title

• H10W70/688

  Flexible insulating substrates · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title