Low power bidirectional bus

Patent metadata

Field	Value
Publication number	US-9935786-B2
Application number	US-201615063124-A
Country	US
Kind code	B2
Filing date	Mar 7, 2016
Priority date	Mar 9, 2015
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.

First claim

The invention claimed is:

1. A method of sending information between first and second modules connected by a signal bus, the method comprising:
generating a clock signal in the first module, and imposing the clock signal on a first line of the signal bus;
transmitting a first pattern of bit values from the second module to the first module on a second line of the signal bus, during first half-periods of each period of said clock signal; and
transmitting a second pattern of bit values from the first module to the second module on the second line of the signal bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal; and the method further comprising at least one of:
in order to transmit information from the first module to the second module, transmitting an altered second pattern of bit values; and
in order to transmit information from the second module to the first module, transmitting an altered first pattern of bit values.

2. A method as claimed in claim 1 , further comprising, in an alternative mode of operation, operating the signal bus as a differential signal bus, wherein the first and second lines of the signal bus operate as the positive signal line and the negative signal line of the differential signal bus.

3. A method as claimed in claim 1 , wherein the second pattern of bit values is the same as the first pattern of bit values, such that transmitting the second pattern of bit values from the first module to the second module requires maintaining the signal level on the second line of the signal bus.

4. A method as claimed in claim 1 , wherein the first pattern of bit values is a Barker code sequence.

5. A method as claimed in claim 1 , wherein the second pattern of bit values is a Barker code sequence.

6. A method as claimed in claim 1 , wherein the altered second pattern of bit values is the second pattern of bit values inverted.

7. A method as claimed in claim 1 , wherein the altered first pattern of bit values is the first pattern of bit values inverted.

8. A method as claimed in claim 1 , comprising performing the method in a low power mode of operation of the second module, wherein the second module is also operable in a normal mode.

9. A method as claimed in claim 8 , comprising switching the second module to the normal mode of operation in response to the first module transmitting information to the second module by transmitting the altered second pattern of bit values.

10. A method as claimed in claim 9 , comprising transmitting information from the first module to the second module by transmitting the altered second pattern of bit values, in response to the second module transmitting information to the first module by transmitting the altered first pattern of bit values.

11. A method as claimed in claim 1 , wherein the first and second modules are provided in a single product.

12. A method as claimed in claim 1 , wherein the first and second modules are provided in first and second devices, respectively, the first and second devices being connected by a wired connection.

13. A method as claimed in claim 12 , wherein the second device is detachably connected to the first device.

14. A method as claimed in claim 13 , wherein the first device is a host device, and the second device is an accessory device.

15. A host module configured to:
generate a clock signal, and impose the clock signal on a first line of a signal bus;
detect a first pattern of bit values transmitted on a second line of the signal bus, during first half-periods of each period of said clock signal;
transmit a second pattern of bit values on the second line of the signal bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal; and being further configured to:
in order to transmit information, to transmit an altered second pattern of bit values; and/or
in order to receive information, to detect an altered first pattern of bit values;

wherein the host module comprises:
a clock output buffer to drive said clock signal onto a first terminal;
an input buffer for receiving a data signal at a second terminal;
controller circuitry for detecting the first pattern of bit values in the received data signal during the first half-periods of each period of said clock signal and generating the second pattern of bit values; and
output buffer circuitry for driving the second pattern of bit values onto the second terminal during the second half-periods of each period of said clock signal;
further wherein the controller circuitry is adapted to transmit said information by altering the second pattern of bit values; and to receive information by detecting said altered first pattern of bit values.

16. A host module as claimed in claim 15 , wherein the second pattern of bit values is the same as the first pattern of bit values, such that transmitting the second pattern of bit values from the master module requires maintaining the signal level on the second terminal.

17. A host device, comprising a host module as claimed in claim 15 .

18. A host device as claimed in claim 17 , wherein the host device comprises an audio device.

19. A host device as claimed in claim 17 , comprising a socket for enabling an accessory device, containing the second module, to connect thereto.

20. An integrated circuit comprising a host module as claimed in claim 15 .

21. An accessory module configured to:
receive a clock signal on a first line of a signal bus;
transmit a first pattern of bit values on a second line of the signal bus, during first half-periods of each period of said clock signal;
receive a second pattern of bit values on the second line of the signal bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal; and being further configured:
in order to receive information, to detect an altered second pattern of bit values; and/or
in order to transmit information, to transmit an altered first pattern of bit values;
wherein the accessory module comprises:
a clock input buffer to receive said clock signal at a first terminal;
an input buffer for receiving a data signal at a second terminal;
controller circuitry for detecting said second pattern of bit values in the received data signal during the second half-periods of each period of said clock signal and generating said first pattern of bit values; and
output buffer circuitry for driving the first pattern of bit values onto the second terminal during the first half-periods of each period of said clock signal;
further wherein said controller circuitry is adapted to transmit the information by altering the first pattern of bit values; and to receive the information by detecting the altered second pattern of bit values.

22. An accessory module as claimed in claim 21 , wherein the controller is adapted to detect the altered second pattern of bit values by detecting that a signal level received on the second terminal during a first half-period of a period of said clock signal has not been maintained from the signal level transmitted on the second terminal by the slave module in the sec

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Zwart Willem
• Bowlerwell John Bruce
• Page Michael
• Boomer Alastair

Classifications

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06F2213/0016

  Inter-integrated circuit (I2C) · CPC title

• G06F13/4291 Primary

  using a clocked protocol · CPC title

• H04L5/1476

  operating bitwise · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title