Circuit for and method of receiving an input signal

Patent metadata

Field	Value
Publication number	US-9935597-B2
Application number	US-201615167197-A
Country	US
Kind code	B2
Filing date	May 27, 2016
Priority date	May 27, 2016
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

A circuit for receiving an input signal is described. The receiver comprises a first receiver input configured to receive a first input of a differential input signal; a second receiver input configured to receive a second input of a differential input signal; a differential pair having an inverting input and a non-inverting input; a first impedance matching element coupled to the differential pair, wherein the first impedance matching element provides DC impedance matching from the inverting input and non-inverting input of the differential pair; and a second impedance matching element coupled to the differential pair, wherein the second impedance matching element provides AC impedance matching from the inverting input and non-inverting input of the differential pair.

First claim

What is claimed is:

1. A circuit for receiving a differential input signal, the circuit comprising:
a first receiver input configured to receive a first input of the differential input signal;
a second receiver input configured to receive a second input of the differential input signal;
a differential pair having an inverting input and a non-inverting input;
a first impedance matching element coupled to the differential pair, wherein the first impedance matching element provides DC impedance matching from the inverting input and non-inverting input of the differential pair; and
a second impedance matching element coupled to the differential pair, wherein the second impedance matching element provides AC impedance matching from the inverting input and non-inverting input of the differential pair.

2. The circuit of claim 1 wherein the first impedance matching element comprises a first resistor.

3. The circuit of claim 2 wherein the first resistor is associated with a first current path from the inverting input of the differential pair.

4. The circuit of claim 3 wherein the first current path comprises a bipolar junction transistor.

5. The circuit of claim 2 further comprising a second resistor associated with a second current path associated with the non-inverting input, wherein the impedance from the inverting input is equal to the impedance from the non-inverting input.

6. The circuit of claim 1 wherein the second current path comprises a bipolar junction transistor.

7. The circuit of claim 1 wherein the second impedance matching element comprises a capacitor.

8. The circuit of claim 1 further comprising a first PMOS transistor associated with the inverting input of the differential pair.

9. The circuit of claim 8 further comprising a second PMOS transistor associated with the non-inverting input of the differential pair.

10. The circuit of claim 9 wherein each of the first PMOS transistor and the second PMOS transistor is a deep N-well transistor.

11. A method of receiving a differential input signal, the method comprising:
configuring a first receiver input to receive a first input of the differential input signal;
configuring a second receiver input to receive a second input of the differential input signal;
implementing a differential pair having an inverting input and a non-inverting input;
coupling a first impedance matching element to the differential pair, wherein the first impedance matching element provides DC impedance matching from the inverting input and non-inverting input of the differential pair; and
coupling a second impedance matching element to the differential pair, wherein the second impedance matching element provides AC impedance matching from the inverting input and non-inverting input of the differential pair.

12. The method of claim 11 wherein coupling the first impedance matching element to the differential pair comprises coupling a first resistor to the differential pair.

13. The method of claim 11 wherein the first resistor is associated with a first current path from the inverting input of the differential pair.

14. The method of claim 13 wherein the first current path comprises a bipolar junction transistor.

15. The method of claim 11 further comprising a second resistor associated with a second current path associated with the non-inverting input, wherein the impedance from the inverting input is equal to the impedance from the non-inverting input.

16. The method of claim 15 wherein the second current path comprises a bipolar junction transistor.

17. The method of claim 11 wherein the second impedance matching element comprises a capacitor.

18. The method of claim 11 further comprising implementing a first PMOS transistor associated with the inverting input of the differential pair.

19. The method of claim 18 further comprising implementing a second PMOS transistor associated with the non-inverting input of the differential pair.

20. The method of claim 19 wherein each of the first PMOS transistor and the second PMOS transistor are deep N-well transistors.

Assignees

• Xilinx Inc

Inventors

• Erdmann Christophe
• Collins Diarmuid
• Cullen Edward
• Cical Ionut C

Classifications

• H03F3/45183

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title

• H03F2203/45288

  Differential amplifier with circuit arrangements to enhance the transconductance · CPC title

• H03F3/45179 Primary

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

• H03F1/56 Primary

  Modifications of input or output impedances, not otherwise provided for · CPC title

• H03F2200/459

  Ripple reduction circuitry being used in an amplifying circuit · CPC title