Power factor correction circuit and driving method thereof

Patent metadata

Field	Value
Publication number	US-9935538-B2
Application number	US-201615077280-A
Country	US
Kind code	B2
Filing date	Mar 22, 2016
Priority date	Mar 23, 2015
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

A power factor correction circuit corrects a filter current flowing through a filter capacitor asymmetrically based on a peak of an input voltage by controlling a switching operation of a power switch, thereby correcting distortion of an input current.

First claim

What is claimed is:

1. A power factor correction circuit comprising:
a filter capacitor; and
a primary side winding connected to the filter capacitor;
a power switch connected to the primary side winding to convert an input voltage into a secondary side output;
an adjustment signal generator to generate an adjustment signal based on an input detection voltage corresponding to a full-wave waveform of an input voltage to the power factor correction circuit, wherein the adjustment signal is asymmetric with respect to a peak of the full-wave waveform of the input voltage; and
a duty generator to control a switching operation of the power switch to correct a filter current flowing through the filter capacitor utilizing the adjustment signal,
wherein the adjustment signal generator comprises:
a reference signal generator to generate an adjustment reference signal synchronized with the input voltage; and
a multiplier to generate the adjustment signal by multiplying an input peak voltage corresponding to the peak of the full-wave waveform of the input voltage by the adjustment reference signal,
wherein the adjustment reference signal has a waveform for correcting distortion of an input current by the filter current.

2. The power factor correction circuit according to claim 1 , wherein the duty generator is to generate an error voltage by correcting a difference between a voltage corresponding to an output voltage and a predetermined reference voltage, and generate a feedback signal by adding the adjustment signal to the error voltage.

3. The power factor correction circuit according to claim 2 , wherein the duty generator is to generate a sawtooth wave signal increasing with a predetermined slope in synchronization with a switching cycle of the power switch and turn off the power switch at a time point in which the sawtooth wave signal reaches the feedback signal.

4. The power factor correction circuit according to claim 1 , wherein the duty generator is synchronized with a switching cycle of the power switch and is to generate a sawtooth wave signal increasing with the controlled slope by controlling variation in slope in a direction reverse to a variation direction of the adjustment signal.

5. The power factor correction circuit according to claim 1 , wherein the duty generator is synchronized with the switching cycle of the power switch and is to generate a sawtooth wave signal increasing with a controlled beginning level by controlling variation in the beginning level in a direction reverse to a variation direction of the adjustment signal.

6. The power factor correction circuit according to claim 1 , wherein the duty generator is to determine a compensation period based on the adjustment signal and control an on-period of the power switch corresponding to the compensation period.

7. The power factor correction circuit according to claim 6 , wherein the duty generator is to calculate the compensation period by dividing a value, obtained by multiplying the adjustment signal by the switching cycle of the power switch, by a value obtained by multiplying the input voltage by the on-period of the power switch.

8. The power factor correction circuit according to claim 7 , wherein the duty generator is to generate a compensation control output by delaying a control output, based on a result of comparison between the feedback signal corresponding to the output voltage and a sawtooth wave signal, by a period corresponding to the sum of at least one switching cycle and the compensation period.

9. The power factor correction circuit according to claim 1 , wherein the duty generator is to generate the feedback signal by controlling a reference voltage according to the adjustment signal and control a switching operation of the power switch based on a result of comparison between a sensing voltage corresponding to a current flowing through the power switch and the feedback signal.

10. The power factor correction circuit according to claim 1 , wherein the duty generator is to generate a compensation sensing voltage by controlling variation in slope of a sensing voltage in a direction reverse to a variation direction of the adjustment signal, and control a switching operation of the power switch based on a result of comparison between the compensation sensing voltage and a reference voltage,
wherein the sensing voltage is a voltage corresponding to a current flowing through the power switch.

11. The power factor correction circuit according to claim 1 , wherein the duty generator is to generate a compensation sensing voltage by controlling variation in a beginning level of the sensing voltage in a direction reverse to a variation direction of the adjustment signal, and control a switching operation of the power switch based on a result of comparison between the compensation sensing voltage and a reference voltage,
wherein the sensing voltage is a voltage corresponding to a current flowing through the power switch.

12. The power factor correction circuit according to claim 1 , wherein the duty generator is to generate a feedback signal based on a result of multiplication of the sum of a reference voltage and the adjustment signal by the switching cycle of the power switch, generate a sensing voltage based on the total amount of a switch current for one switching cycle of the power switch, and turn off the power switch based on a result of comparison between the sensing voltage and the feedback signal.

13. A power factor correction circuit comprising:
a filter capacitor;
an adjustment signal generator to generate an adjustment signal based on an input detection voltage corresponding to a full-wave waveform of an input voltage to the power factor correction circuit, wherein the adjustment signal is asymmetric with respect to a peak of the full-wave waveform of the input voltage; and
a power supply comprising a power switch electrically connected to the filter capacitor and converting an input voltage into output power using the power switch,
wherein the power factor correction circuit is to control a switching operation of the power switch to correct a filter current flowing through the filter capacitor utilizing the adjustment signal,
wherein the adjustment signal generator comprises:
a reference signal generator to generate an adjustment reference signal synchronized with the input voltage; and
a multiplier to generate the adjustment signal by multiplying an input peak voltage corresponding to the peak of the full-wave waveform of the input voltage by the adjustment reference signal,
wherein the adjustment reference signal has a waveform for correcting distortion of an input current by the filter current.

14. The power factor correction circuit according to claim 13 , further comprising
a duty generator to generate an error voltage by correcting a difference between a voltage corresponding to an output voltage and a predetermined reference voltage, and generate a feedback signal by adding the adjustment signal to the error voltage.

15. A method for driving a power factor correction circuit comprising a power supply electrically connected to a filter capacitor, the method comprising:
generating an adjustment signal based on an input detection voltage corresponding to a full-wave waveform of an input voltage of the power supply, wherein the adjustment signal is asymmetric with respect to a peak of the full-wave waveform of the input voltage; and
correcting a filter current flowing through the filter capacitor by controlling a switching operation of a power switch of the power supply utilizing the adjustment signal,
wherei

Assignees

• Fairchild Korea Semiconductor Ltd
• Semiconductor Components Ind Llc

Inventors

• Eum Hyun-Chul
• Kim Taesung
• Park In-Ki
• Kim Young-Jong

Classifications

• H02M1/4258 Primary

  using a single converter stage both for correction of AC input power factor and generation of a regulated and galvanically isolated DC output voltage (H02M1/4241 takes precedence) · CPC title

• H02M1/12

  Arrangements for reducing harmonics from AC input or output · CPC title

• H02M3/33523

  with galvanic isolation between input and output of both the power stage and the feedback loop · CPC title

• Y02B70/126

  Cross-Sectional Technologies · mapped topic

• Y02P80/112

  Cross-Sectional Technologies · mapped topic