Transistor and display device comprising oxide semiconductor layer

Patent metadata

Field	Value
Publication number	US-9935202-B2
Application number	US-201213528009-A
Country	US
Kind code	B2
Filing date	Jun 20, 2012
Priority date	Sep 16, 2009
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

To provide a transistor having a favorable electric characteristics and high reliability and a display device including the transistor. The transistor is a bottom-gate transistor formed using an oxide semiconductor for a channel region. An oxide semiconductor layer subjected to dehydration or dehydrogenation through heat treatment is used as an active layer. The active layer includes a first region of a superficial portion microcrystallized and a second region of the rest portion. By using the oxide semiconductor layer having such a structure, a change to an n-type, which is attributed to entry of moisture to the superficial portion or elimination of oxygen from the superficial portion, and generation of a parasitic channel can be suppressed. In addition, contact resistance between the oxide semiconductor layer and source and drain electrodes can be reduced.

First claim

What is claimed is:

1. A transistor comprising:
a gate electrode layer;
a gate insulating layer adjacent to the gate electrode layer;
an oxide semiconductor layer adjacent to the gate electrode layer with the gate insulating layer therebetween, the oxide semiconductor layer including a channel region; and
an oxide insulating layer in contact with the oxide semiconductor layer, wherein the oxide semiconductor layer is located between the gate insulating layer and the oxide insulating layer,
wherein the oxide semiconductor layer includes a first metal, a second metal, and a third metal,
wherein the first metal is indium, the second metal is zinc, and the third metal is a different metal from indium and zinc, and
wherein at least part of the channel region includes crystals which are c-axis-oriented in a direction perpendicular to a surface of the oxide semiconductor layer.

2. The transistor according to claim 1 , wherein the oxide semiconductor layer is formed over the gate electrode layer.

3. The transistor according to claim 1 , wherein the part of the channel region includes a superficial portion of the oxide semiconductor layer.

4. The transistor according to claim 1 , wherein a size of the crystals is 20 nm or less in a direction along a short axis direction.

5. The transistor according to claim 1 , wherein the crystals are microcrystals.

6. The transistor according to claim 1 , wherein the gate insulating layer is a laminate film of silicon nitride and silicon oxynitride.

7. The transistor according to claim 1 , wherein the oxide semiconductor layer is a laminate layer.

8. The transistor according to claim 1 , further comprising a source electrode and a drain electrode each adjacent to the oxide semiconductor layer,
wherein each of the source electrode and the drain electrode has a three-layer structure in which aluminum is sandwiched by titanium.

9. The transistor according to claim 1 , wherein the third metal is gallium.

10. The transistor according to claim 1 , wherein the third metal is selected from gallium, aluminum, manganese, cobalt, and tin.

11. A transistor comprising:
a gate electrode layer;
a gate insulating layer over the gate electrode layer;
an oxide semiconductor layer over the gate electrode layer with the gate insulating layer therebetween, the oxide semiconductor layer including a channel region;
a source electrode over the oxide semiconductor layer;
a drain electrode over the oxide semiconductor layer;
an oxide insulating layer in contact with the oxide semiconductor layer, wherein the oxide semiconductor layer is located between the gate insulating layer and the oxide insulating layer,
wherein the oxide semiconductor layer includes a first metal, a second metal, and a third metal,
wherein the first metal is indium, the second metal is zinc, and the third metal is a different metal from indium and zinc, and
wherein at least part of the channel region includes crystals which are c-axis-oriented in a direction perpendicular to a surface of the oxide semiconductor layer.

12. The transistor according to claim 11 , wherein the part of the channel region includes a superficial portion of the oxide semiconductor layer.

13. The transistor according to claim 11 , wherein a size of the crystals is 20 nm or less in a direction along a short axis direction.

14. The transistor according to claim 11 , wherein the crystals are microcrystals.

15. The transistor according to claim 11 , wherein the gate insulating layer is a laminate film of silicon nitride and silicon oxynitride.

16. The transistor according to claim 11 , wherein the oxide semiconductor layer is a laminate layer.

17. The transistor according to claim 11 , wherein each of the source electrode and the drain electrode has a three-layer structure in which aluminum is sandwiched by titanium.

18. The transistor according to claim 11 , wherein the third metal is gallium.

19. The transistor according to claim 11 , wherein the third metal is selected from gallium, aluminum, manganese, cobalt, and tin.

20. A transistor comprising:
a gate electrode layer;
a gate insulating layer over the gate electrode layer;
an oxide semiconductor layer over the gate electrode layer with the gate insulating layer therebetween, the oxide semiconductor layer including a channel region;
a source electrode over the oxide semiconductor layer;
a drain electrode over the oxide semiconductor layer;
an oxide insulating layer in contact with the oxide semiconductor layer, wherein the oxide semiconductor layer is located between the gate insulating layer and the oxide insulating layer,
wherein the oxide semiconductor layer includes a first metal, a second metal, and a third metal,
wherein the first metal is indium, the second metal is zinc, and the third metal is a different metal from indium and zinc, and
wherein at least part of the channel region includes crystals which are c-axis-oriented in a direction perpendicular to a surface of the oxide semiconductor layer,
wherein an entirety of the oxide semiconductor layer overlaps with the gate electrode layer.

21. The transistor according to claim 20 , wherein the gate electrode layer extends beyond an outer edge of the oxide semiconductor layer.

22. The transistor according to claim 20 , wherein the part of the channel region includes a superficial portion of the oxide semiconductor layer.

23. The transistor according to claim 20 , wherein a size of the crystals is 20 nm or less in a direction along a short axis direction.

24. The transistor according to claim 20 , wherein the crystals are microcrystals.

25. The transistor according to claim 20 , wherein the gate insulating layer is a laminate film of silicon nitride and silicon oxynitride.

26. The transistor according to claim 20 , wherein the oxide semiconductor layer is a laminate layer.

27. The transistor according to claim 20 , wherein each of the source electrode and the drain electrode has a three-layer structure in which aluminum is sandwiched by titanium.

28. The transistor according to claim 20 , wherein the third metal is gallium.

29. The transistor according to claim 20 , wherein the third metal is selected from gallium, aluminum, manganese, cobalt, and tin.

Assignees

• Yamazaki Shunpei
• Sakakura Masayuki
• Watanabe Ryosuke
• Sakata Junichiro
• Akimoto Kengo
• Miyanaga Akiharu
• Hirohashi Takuya
• Kishida Hideyuki
• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Sakakura Masayuki
• Watanabe Ryosuke
• Sakata Junichiro
• Akimoto Kengo
• Miyanaga Akiharu
• Hirohashi Takuya
• Kishida Hideyuki

Classifications

• G02F1/1362

  Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)} · CPC title

• H01L29/7869 Primary

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic

• H01L29/78693

  Electricity · mapped topic

• H01L29/78618

  Electricity · mapped topic