Substrate design for semiconductor packages and method of forming same

Patent metadata

Field	Value
Publication number	US-9935090-B2
Application number	US-201514622517-A
Country	US
Kind code	B2
Filing date	Feb 13, 2015
Priority date	Feb 14, 2014
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

An embodiment device includes a first die, a first molding compound extending along sidewalls of the first die, and one or more first redistribution layers (RDLs) on the first die and the first molding compound. The device further includes a device package comprising a plurality of second dies, wherein the device package is bonded to an opposing surface of the one or more first RDLs as the first die and the first molding compound. A package substrate is bonded to the opposing surface of the one or more first RDLs. The package substrate is electrically connected to the first die and the plurality of second dies.

First claim

What is claimed is:

1. A device comprising:
a first die having contact pads on a surface of the first die;
a first molding compound extending along sidewalls of the first die;
one or more first redistribution layers (RDLs) on the first die and the first molding compound, the one or more first RDLs comprising conductive features formed in one or more polymer layers, the conductive features contacting the contact pads of the first die, the first molding compound coterminous with the one or more first RDLs;
a device package comprising a plurality of second dies and one or more second RDLs, wherein the device package is bonded to an opposing surface of the one or more first RDLs as the first die and the first molding compound with first copper connectors extending from a first side of the one or more second RDLs, wherein the one or more second RDLs electrically connect each one of the plurality of second dies to the one or more first RDLs, wherein the one or more first RDLs extend laterally past edges of the one or more second RDLs, wherein the plurality of second dies each comprise second copper connectors contacting a second side of the one or more second RDLs opposite the first side of the one or more second RDLs, the first copper connectors being larger than the second copper connectors;
a package substrate bonded to the opposing surface of the one or more first RDLs, wherein the package substrate is electrically connected to the first die and the plurality of second dies; and
an underfill disposed between the one or more first RDLs and the one or more second RDLs, the underfill contacting the first copper connectors.

2. The device of claim 1 , wherein the one or more second RDLs redistribute electrical connections from the plurality of second dies to the first copper connectors, the first copper connectors being a plurality of control collapse chip connection (C 4 ) bumps or a plurality of ball grid array (BGA) balls.

3. The device of claim 1 , wherein the plurality of second dies comprises at least two dies disposed laterally adjacent each other.

4. The device of claim 1 , wherein the plurality of second dies comprises at least two die stacks disposed laterally adjacent each other.

5. The device of claim 1 , wherein the device package further comprises a second molding compound extending along sidewalls of the plurality of second dies, top surfaces of the second connectors being planar with a top surface of the second molding compound.

6. The device of claim 5 , wherein the second molding compound at least partially encases the plurality of second dies.

7. The device of claim 5 , wherein at least a surface of the plurality of second dies and the top surfaces of the second connectors are exposed by the second molding compound.

8. The device of claim 1 , wherein the package substrate comprises a through hole, and the device package is at least partially disposed in the through hole, the through hole being round.

9. A device comprising:
a first die comprising contact pads;
first fan-out redistribution layers (RDLs) formed on the first die, the first fan-out RDLs comprising conductive features formed in one or more polymer layers, the conductive features contacting the contact pads of the first die, wherein the first fan-out RDLs extend laterally past edges of the first die;
a first molding compound contacting the first fan-out RDLs and sidewalls of the first die, the first molding compound coterminous with the first fan-out RDLs;
a device package bonded to an opposing side of the first fan-out RDLs as the first die with first connectors, wherein the device package comprises:
a second die having a first surface and a second surface opposite the first surface, one or more first passivation layers on the first surface of the second die, the second die having second connectors smaller than the first connectors;
a third die disposed laterally adjacent the second die, the third die having a first surface and a second surface opposite the first surface, one or more second passivation layers on the first surface of the third die, the third die having third connectors smaller than the first connectors;
a second molding compound extending along sidewalls of the second die and the third die, the second molding compound having a first surface and a second surface, the first surface of the second molding compound being level with top surfaces of the one or more first passivation layers and top surfaces of the one or more second passivation layers, the second surface of the second molding compound being level with the second surface of the second die and the second surface of the third die; and
second fan-out RDLs connecting the second connectors and the third connectors to the first connectors;

an underfill between the first fan-out RDLs and the second fan-out RDLs, the underfill contacting the first connectors; and
a package substrate bonded to the first fan-out RDLs.

10. The device of claim 9 , wherein the second die is disposed in a first die stack comprising a first plurality of vertically stacked dies, wherein the third die is disposed in a second die stack comprising a second plurality of vertically stacked dies, and wherein the first die stack is disposed laterally adjacent the second die stack.

11. The device of claim 9 , wherein the second fan-out RDLs extends laterally past edges of the second die and the third die, wherein the second fan-out RDLs physically contact the one or more first passivation layers and the one or more second passivation layers.

12. The device of claim 9 , wherein the second fan-out RDLs redistribute electrical connections from the second die and the third die to the first connectors, the first connectors being a plurality of control collapse chip connection (C 4 ) bumps or a plurality of ball grid array (BGA) balls, and wherein the plurality of C 4 bumps or the plurality of BGA balls bonds the second fan-out RDLs of the device package to the first fan-out RDLs.

13. The device of claim 9 , further comprising a through-hole extending through the package substrate, wherein the device package is at least partially disposed in the through-hole.

14. A method comprising:
forming a first molding compound around and on a first die;
planarizing the first molding compound to expose contact pads of the first die;
forming one or more first fan-out redistribution layers (RDLs) on the first die and the first molding compound, conductive features of the first fan-out RDLs contacting the contact pads of the first die;
forming a device package, wherein forming the device package comprises:
disposing a second die on a carrier, the second die including first conductive pillars and a first passivation layer around the first conductive pillars;
disposing a third die adjacent the second die on the carrier, the third die including second conductive pillars and a second passivation layer around the second conductive pillars;
forming a second molding compound around the first passivation layer, the second passivation layer, the second die, and the third die;
planarizing the second molding compound, the first passivation layer, and the second passivation layer to expose the first conductive pillars and the second conductive pillars;
removing the carrier after the planarizing to expose back surfaces of the second die and the third die; and
forming one or more second fan-out RDLs over the second die, the third die, and the second molding compound, wherein the one or more second fan-out RDLs are electrically connected to the first conductive pillars and the second conductive pillars;

bonding the one or more second fan-ou

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Cheng Jung Wei
• Wang Tsung-Ding
• Lee Chien-Hsun

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title