Package assembly with gathered insulated wires

Patent metadata

Field	Value
Publication number	US-9935036-B2
Application number	US-201515036385-A
Country	US
Kind code	B2
Filing date	Jun 26, 2015
Priority date	Jun 26, 2015
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

Some embodiments of the present disclosure describe an integrated circuit (IC) package assembly having first, second, and third insulated wires wire bonded with die pads on an IC die, with an outer surface of the second insulated wire located at a distance of less than an outer cross-sectional diameter of the second insulated wire from an outer surface of the first insulated wire at a first location and located at a distance of less than the outer cross-sectional diameter from an outer surface of the third insulated wire at a second location. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. An integrated circuit (IC) package assembly comprising:
an IC die;
a first insulated wire having a first end wire bonded with the IC die at a first die pad;
a second insulated wire having an outer cross-sectional diameter and a first end wire bonded with the IC die at a second die pad; and
a third insulated wire having a first end wire bonded with the IC die at a third die pad, wherein:
the first, second, and third die pads are disposed on the IC die and are separate from each other;
an outer surface of the second insulated wire is located at a distance of less than the outer cross-sectional diameter of the second insulated wire from an outer surface of the first insulated wire at a first location; and
the outer surface of the second insulated wire is located at a distance of less than the outer cross-sectional diameter of the second insulated wire from an outer surface of the third insulated wire at a second location.

2. The IC package assembly of claim 1 , wherein:
the first, second, and third insulated wires extend in parallel along a gathered region;
the first insulated wire touches both the second insulated wire and the third insulated wire along at least a portion of the gathered region; and
the second insulated wire touches both the first insulated wire and the third insulated wire along at least a portion of the gathered region.

3. The IC package assembly of claim 2 , wherein the second insulated wire is shorter than the first insulated wire and the third insulated wire.

4. The IC package assembly of claim 2 , wherein the first insulated wire is a ground wire and the second and third insulated wires are a differential signal wire pair.

5. The IC package assembly of claim 1 , further comprising a fourth insulated wire having a first end wire bonded with the IC die at a fourth die pad, wherein:
the first, second, third, and fourth insulated wires extend in parallel along a gathered region;
the first insulated wire touches the second insulated wire along at least a portion of the gathered region; and
the third insulated wire touches both the second insulated wire and the fourth insulated wire along at least a portion of the gathered region.

6. The IC package assembly of claim 5 , wherein:
the first, second, third, and fourth die pads are spaced apart in a first direction; and
at least one of the first, second, third, and fourth die pads are spaced apart in a second direction with respect to at least one of the other of the first, second, third, and fourth die pads.

7. The IC package assembly of claim 5 , wherein the first and fourth insulated wires are ground wires and the second and third insulated wires are a differential signal wire pair.

8. The IC package assembly of claim 2 , wherein at least one of the first, second, and third insulated wires is less than or equal to 700 microns in length.

9. The IC package assembly of claim 2 , further comprising a package substrate, wherein:
the first insulated wire includes a second end wire bonded with the package substrate at a first substrate pad;
the second insulated wire includes a second end wire bonded with the package substrate at a second substrate pad; and
the third insulated wire includes a second end wire bonded with the package substrate at a third substrate pad.

10. The IC package assembly of claim 2 , further comprising a printed circuit board (PCB), wherein:
the first insulated wire includes a second end wire bonded with the PCB at a first PCB pad;
the second insulated wire includes a second end wire bonded with the PCB at a second PCB pad; and
the third insulated wire includes a second end wire bonded with the PCB at a third PCB pad.

11. A method of fabricating an integrated circuit (IC) package assembly, the method comprising:
providing an IC die;
wire bonding a first end of a first insulated wire to the IC die at a first pad;
wire bonding a first end of a second insulated wire having an outer cross-sectional diameter to the IC die at a second pad;
wire bonding a first end of a third insulated wire to the IC die at a third pad; and
gathering the first, second, and third wires together along a gathered region, wherein:
the first, second, and third pads are separate from each other;
an outer surface of the second insulated wire is located at a distance of less than the outer cross-sectional diameter of the second insulated wire from an outer surface of the first insulated wire along at least a portion of the gathered region; and
the outer surface of the second insulated wire is located at a distance of less than the outer cross-sectional diameter of the second insulated wire from an outer surface of the third insulated wire along at least a portion of the gathered region.

12. The method of fabricating an IC package assembly of claim 11 , wherein:
the first, second, and third insulated wires extend in parallel along the gathered region; and
the first insulated wire touches both the second insulated wire and the third insulated wire along at least a portion of the gathered region.

13. The method of fabricating an IC package assembly of claim 12 , wherein the first insulated wire is a ground wire and the second and third insulated wires are a differential signal wire pair.

14. The method of fabricating an IC package assembly of claim 11 , further comprising wire bonding a first end of a fourth insulated wire to the IC at a fourth die pad, wherein:
the first, second, third, and fourth insulated wires extend in parallel along a gathered region;
the first insulated wire touches the second insulated wire along at least a portion of the gathered region; and
the third insulated wire touches both the second insulated wire and the fourth insulated wire along at least a portion of the gathered region.

15. The method of fabricating an IC package assembly of claim 14 , wherein:
the first, second, third, and fourth die pads are spaced apart in a first direction; and
at least one of the first, second, third, and fourth die pads are spaced apart in a second direction with respect to at least one of the other of the first, second, third, and fourth die pads.

16. The method of fabricating an IC package assembly of claim 14 , wherein the first and fourth insulated wires are ground wires and the second and third insulated wires are a differential signal wire pair.

17. The method of fabricating an IC package assembly of claim 12 , wherein at least one of the first, second, and third insulated wires is less than or equal to 700 microns in length.

18. The method of fabricating an IC package assembly of claim 12 , further comprising:
wire bonding a second end of the first insulated wire to a package substrate at a first substrate pad;
wire bonding a second end of the second insulated wire to a package substrate at a second substrate pad;
wire bonding a second end of the third insulated wire to a package substrate at a third substrate pad.

19. A computing device comprising:
a circuit board; and
an integrated circuit (IC) package assembly coupled with the circuit board, the IC package assembly including:
an IC die;
a first insulated wire having a first end wire bonded with the IC die at a first die pad;
a second insulated wire having an outer cross-sectional diameter and a first end wire bonded with the IC die at a second die pad; and
a third insulated wire having a first end wire bonded with the IC die at a third die pad, wherein:
the first, second, and third die pads are disposed on the IC die;
an outer

Assignees

• Intel Corp

Inventors

• Ouyang Gong
• Lee Beom-Taek

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title