Rank determination

Patent metadata

Field	Value
Publication number	US-9934862-B2
Application number	US-201715424065-A
Country	US
Kind code	B2
Filing date	Feb 3, 2017
Priority date	Apr 15, 2014
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

Technologies are generally provided for methods and circuitry to rank a large number of cells in a timeframe of about one sense cycle. In some examples, an architecture may be implemented to rank memory cells such as volatile memories, non-volatile memories, and other types of data storage devices, where there may not be an equivalent to threshold voltage. In other examples, an arbitrary group of circuits, such as in neural networks where there may not be an equivalent control gate to set the timing resolution, may be ranked. Relative sense timing may be used to rank the cells having different current carrying abilities. A ramped gate voltage may be used to control the timing resolution and to reduce contention between close separate cells. Digital logic may be used to latch and/or record the rank information.

First claim

What is claimed is:

1. A method to determine rank of a plurality of circuits, the method comprising:
determining relative sense timing for the plurality of circuits, wherein at least one circuit of the plurality of circuits has a different current carrying capability relative to other circuits of the plurality of circuits, by:
turning on a reset line to discharge bit lines that correspond to columns of memory cells within the plurality of circuits;
applying a voltage to a selec…

Assignees

• Empire Technology Dev Llc

Inventors

• Ma Yanjun
• Kan Edwin

Classifications

• G11C16/32

  Physics · mapped topic

• G11C13/0004

  Physics · mapped topic

• G11C16/24

  Physics · mapped topic

• G11C16/0408

  Physics · mapped topic

• G11C16/26 Primary

  Physics · mapped topic