Multi-communication device in a memory system

Patent metadata

Field	Value
Publication number	US-9934830-B2
Application number	US-201615298335-A
Country	US
Kind code	B2
Filing date	Oct 20, 2016
Priority date	Nov 18, 2015
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

In a memory module including a memory device and a filter, the memory device operates with a clock of a reference frequency. The filter receives a multiplexed signal from a host and filters a signal of a frequency band from the multiplexed signal. The frequency band includes the reference frequency and the signal of the frequency band is provided to the memory device.

First claim

What is claimed is:

1. A memory module, comprising:
a memory device configured to operate with a clock of a reference frequency; and
a filter configured to receive a multiplexed signal from a host and to filter a signal of a frequency band from the multiplexed signal,
wherein the frequency hand comprises the reference frequency, and
the signal of the frequency band is provided to the memory device.

2. The memory module of claim 1 , wherein the multiplexed signal comprises at least one of data, a command, an address, or a clock signal transferred at the frequency band, and
the data, the command, the address, and the clock signal are transferred to the filter through distinct signal paths.

3. The memory module of claim 1 , further comprising:
a demodulation device configured to demodulate signals passing through the filter and to transfer demodulated signals to the memory device.

4. The memory module of claim 1 , further comprising:
a path selector configured to change a path of a filtered first signal of the multiplexed signal to a path of a filtered second signal of the multiplexed signal in response to setting information from the host.

5. The memory module of claim 1 , further comprising:
a demodulation device configured to demodulate signals passing through the filter and to transfer demodulated signals to the memory device; and
a path selector configured to change a path of a filtered first signal of the multiplexed signal to a path of a filtered second signal of the multiplexed signal in response to setting information from the host.

6. The memory module of claim 1 , wherein the memory module is connected to the host and has a dual in-line memory module (DIMM) structure.

7. A memory module, comprising:
a first memory device configured to operate with a clock of a first reference frequency;
a second memory device configured to operate with a clock of a second reference frequency that is different from the first reference frequency;
a first filter configured to receive a multiplexed signal from a host and to filter a signal of a first frequency band, comprising the first reference frequency, from the multiplexed signal; and
a second filter configured to receive the multiplexed signal from the host and to filter a signal of a second frequency band, comprising the second reference frequency, from the multiplexed signal,
wherein the signal of the first frequency band is provided to the first memory device and the signal of the second frequency band is provided to the second memory device.

8. The memory module of claim 7 , wherein the multiplexed signal comprises at least one of first data, a first command, a first address, or a first clock signal transferred at the first frequency band, and
the first data, the first command, the first address, and the first clock signal are transferred to the first filter through distinct signal paths.

9. The memory module of claim 8 , wherein the multiplexed signal further comprises at least one of second data, a second command, a second address, or a second clock signal transferred at the second frequency band, and
the second data, the second command, the second address, and the second clock signal are transferred to the second filter through distinct signal paths.

10. The memory module of claim 7 , further comprising:
a demodulation device configured to demodulate signals passing through the first filter or the second filter and to transfer demodulated signals to the first memory device or the second memory device.

11. The memory module of claim 7 , further comprising:
a first path selector configured to change a path of a first signal, passing through the first filter, of the multiplexed signal to a path of a. second signal, passing through the first filter, of the multiplexed signal, in response to setting information from the host.

12. The memory module of claim 11 , further comprising:
a second path selector configured to change a path of a third signal, passing through the second filter, of the multiplexed signal to a path of a fourth signal, passing through the second filter, of the multiplexed signal, in response to the setting information from the host.

13. The memory module of claim 7 , further comprising:
a demodulation device configured to demodulate signals passing through the first filter or the second filter and to transfer the demodulated signals to the first memory device or the second memory device;
a first path selector configured to change a path of a first signal, passing through the first filter, of the multiplexed signal to a path of a second signal, passing through the first filter, of the multiplexed signal, in response to setting information from the host; and
a second path selector configured to change a path of a third signal, passing through the second filter, of the multiplexed signal to a path of a fourth signal, passing through the second filter, of the multiplexed signal, in response to the setting information from the host.

14. The memory module of claim 7 , wherein the memory module is connected to the host and has a dual in-line memory module (DIMM) structure.

15. The memory module of claim 7 , wherein the first memory device or the second memory device comprises at least one of a dynamic random access memory (DRAM), a static random access memory (SRAM), a thyristor RAM (TRAM), a zero capacitor RAM (Z-RAM), a twin transistor RAM (TTRAM), a magnetoelectric RAM (MRAM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a spin-transfer torque MRAM (STT-MRAM), a conductive bridging RAM (CBRAM), a ferroelectric RAM (FeRAM), a phase change RAM (PRAM), a resistive RAM (RRAM), a nanotube RRAM (RRAM), a polymer RAM (PoRAM), a nano-floating gate memory (NFGM), a holographic memory, a molecular electronic memory device, or an insulator resistance change memory.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jongmin
• Ko Tae-Kyeong
• Kim Do-Han
• Moon Sungup
• Won Kyoyeon

Classifications

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C7/1012 Primary

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title

• G11C7/02

  with means for avoiding parasitic signals · CPC title