Methods and systems for accessing storage using a network interface card

Patent metadata

Field	Value
Publication number	US-9934177-B2
Application number	US-201514667485-A
Country	US
Kind code	B2
Filing date	Mar 24, 2015
Priority date	Nov 4, 2014
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

Methods and systems for efficiently processing input/output requests are provided. A network interface card (NIC) is coupled to a storage device via a peripheral link and accessible to a processor of a computing device executing instructions out of a memory device. The NIC is configured to receive a read/write request to read/write data; translate the read/write request to a storage device protocol used by the storage device coupled to the NIC; notify the storage device of the read/write request, without using the processor of the computing device, where the storage device reads/writes the data and notifies the NIC; and then the NIC prepares a response to the read/write request without having to use the processor of the computing device.

First claim

What is claimed is:

1. A machine-implemented method, comprising:
receiving a write request at a network interface card (NIC) to write data, the NIC coupled to a storage device via a peripheral link, and the NIC accessible to a processor of a computing device executing instructions out of a memory device;
translating the write request by the NIC from a network protocol to a storage device protocol, the storage device protocol used by the storage device that is coupled to the NIC by the peripheral link, for storing data;
temporarily storing the data for the write request at the memory device by the NIC;
notifying the storage device by the NIC of the write request and the data for the write request temporarily stored at the memory device, using the peripheral link for peer to peer communication, without using the processor of the computing device;
obtaining the data for the write request from the memory device by a memory controller of the storage device and then writing the data for the write request by the memory controller to the storage device;
notifying the NIC directly by the storage device that the data for the write request has been written using the peripheral link for peer to peer communication;
preparing a response to the write request by the NIC without having to use the processor of the computing device; and
sending a completion message to the storage device by the NIC after the response is sent and then releasing by the storage device a completion queue entry associated with the write request, such that the released completion queue entry is reused for other requests.

2. The method of claim 1 , wherein to communicate with the storage device, the NIC generates a doorbell message using a message signaled interrupt (MSI-X) for an address space of the storage device.

3. The method of claim 1 , wherein the storage device is a non-volatile memory express (NVMe) based solid state storage device.

4. The method of claim 1 , wherein the memory device maintains a submission queue for the NIC to post a message for the storage device via the peripheral link and the storage device accesses the memory device to obtain the message via the peripheral link.

5. The method of claim 1 , wherein the memory device maintains a completion queue for the storage device to post a completion message for the NIC and the NIC accesses the memory device to obtain the completion message via the peripheral link.

6. The method of claim 1 , further comprising:
terminating a network protocol processing by the NIC prior to translating the write request; and
validating the write request for authorized access.

7. The method of claim 1 , wherein to communicate with the NIC, the storage device generates a doorbell message using a message signaled interrupt (MSI-X) for an address space of the NIC assigned at the memory device.

8. A machine-implemented method, comprising:
receiving a read request at a network interface card (NIC) to read data, the NIC coupled to a storage device via a peripheral link and the NIC accessible to a processor of a computing device executing instructions out of a memory device;
parsing the read request by the NIC and determining by the NIC a destination address of the data for the read request;
validating the read request by the NIC;
determining by the NIC if there is a cache hit indicating that data for the read request is stored at a cache maintained by the memory device;
translating the read request by the NIC to a storage device protocol used by the storage device coupled to the NIC for storing the data, when there is no cache hit;
notifying the storage device of the read request by the NIC using the peripheral link for peer to peer communication, without using the processor of the computing device;
writing the data for the read request from the storage device to the memory device by a memory controller of the storage device using the peripheral link;
notifying the NIC directly by the storage device that data has been written at the memory device using the peripheral link for peer to peer communication;
obtaining the data for the read request from the memory device by the NIC; and
preparing a response to the read request by the NIC with the data obtained from the memory device, without having to use the processor of the computing device.

9. The method of claim 8 , wherein to communicate with the storage device, the NIC generates a doorbell message using a message signaled interrupt (MSI-X) for an address space of the storage device.

10. The method of claim 8 , wherein the storage device is a non-volatile memory express (NVMe) solid state storage device.

11. The method of claim 8 , wherein the NIC obtains data for the read request from the memory device, when there is a cache hit, without having to access the storage device.

12. The method of claim 8 , wherein the memory device maintains a submission queue for the NIC to post a message for the storage device and the storage device accesses the memory device to obtain the message.

13. The method of claim 8 , wherein the memory device maintains a completion queue for the storage device to post a completion message for the NIC and the NIC accesses the memory device to obtain the completion message.

14. The method of claim 8 , wherein to communicate with the NIC, the storage device generates a doorbell message using a message signaled interrupt (MSI-X) for an address space of the NIC.

15. A system comprising:
a network interface card (NIC) coupled to a storage device via a peripheral link and accessible to a processor of a computing device executing instructions out of a memory device, where the NIC is configured to receive a write request to write data; translate the write request from a network protocol to a storage device protocol used by the storage device coupled to the NIC by a peripheral link for storing data; temporarily store the data for the write request at the memory device; notify the storage device of the write request and the data for the write request stored at the memory device, using the peripheral link for peer to peer communication, without using the processor of the computing device, where a memory controller of the storage device obtains the data for the write request from the memory device, writes the data at the storage device and notifies the NIC that the data for the write request has been written using the peripheral link for peer to peer communication; and then the NIC prepares a response to the write request without having to use the processor of the computing device; sends a completion message to the storage device and the storage device releases a completion queue entry associated with the write request, such that the released completion queue entry is reused for other requests.

16. The system of claim 15 , wherein to communicate with the storage device, the NIC generates a doorbell message using a message signaled interrupt (MSI-X) for an address space of the storage device.

17. The system of claim 15 , wherein the storage device is a non-volatile memory express (NVMe) solid state storage device.

18. The system of claim 15 , wherein the memory device maintains a submission queue for the NIC to post a message for the storage device via the peripheral link and the storage device accesses the memory device to obtain the message via the peripheral link.

19. The system of claim 15 , wherein the memory device maintains a completion queue for the storage device to post a completion message for the NIC and the NIC accesses the memory device to obtain the

Assignees

• Qlogic Corp
• Cavium Inc

Inventors

• Goren Nir
• Shalom Rafi
• Carmona Kobby

Classifications

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/067

  Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS] · CPC title

• G06F12/1081

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• G06F2212/2532

  comprising a plurality of modules · CPC title