Parallelization compiling method, parallelization compiler, and vehicular device

Patent metadata

Field	Value
Publication number	US-9934012-B2
Application number	US-201615083526-A
Country	US
Kind code	B2
Filing date	Mar 29, 2016
Priority date	Mar 31, 2015
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

A parallelization compiling method for generating a segmented program from a sequential program includes assigning macro tasks included in the sequential program to cores included in the multi-core processor in order to generate the segmented program, adding a new macro task to the sequential program or deleting one of the macro tasks from the sequential program, and compiling the sequential program into the segmented program in response to the adding of the new macro task under a condition that the macro tasks assigned to the cores do not migrate among the cores or compiling the sequential program into the segmented program in response to the deleting of the one of the macro tasks under a condition that remains of the macro tasks assigned to the cores do not migrate among the cores.

First claim

What is claimed is:

1. A parallelization compiling method for generating a segmented program, which is executable by a multi-core processor, from a sequential program, which is executable by a single-core processor, by parallelizing the sequential program,
the parallelization compiling method comprising:
assigning one or more macro tasks included in the sequential program to a plurality of cores included in the multi-core processor in order to generate the segmented program;
adding a new macro task to the sequential program or deleting one of the one or more macro tasks from the sequential program; and
assigning again the sequential program, to which addition or deletion of the macro task is carried out, to the plurality of cores under a condition that the one or more macro tasks previously assigned to the plurality of cores do not migrate among the plurality of cores,
wherein among the plurality of cores, a target core to which the new macro task is assigned is determined so that an execution duration of the segmented program after adding the new macro task has a minimum value compared with a case in which the new macro task is assigned to another core under a condition that the new macro task has no dependency relation with the one or more macro tasks included in the sequential program.

2. The parallelization compiling method according to claim 1 , wherein,
when the new macro task is added to the sequential program, in compiling of the sequential program into the segmented program, an assignment of the one or more macro tasks to the plurality of cores is maintained without change and a target core to which the new macro task is assigned among the plurality of cores is determined based on an execution duration of the segmented program to which the new macro task is added.

3. The parallelization compiling method according to claim 1 , wherein,
when the one of the one or more macro tasks is to be deleted from the sequential program, in compiling of the sequential program into the segmented program, a deletion of the one of the one or more macro tasks is carried out and an assignment of the remains of the one or more macro tasks to the plurality of cores is maintained without change.

4. The parallelization compiling method according to claim 3 , wherein,
when deleting the one of the one or more macro tasks from the sequential program, information indicating a data dependency related to the one of the one or more macro tasks is remained without deletion.

5. A parallelization compiler stored in a non-transitory tangible computer readable storage medium as a program product, wherein the parallelization compiler generates a segmented program, which is executable by a multi-core processor, from a sequential program, which is executable by a single-core processor, by parallelizing the sequential program,
the parallelization compiler comprising instructions to be executed by a parallelization compiling device, the instructions for implementing:
assigning one or more macro tasks included in the sequential program to a plurality of cores included in the multi-core processor in order to generate the segmented program;
adding a new macro task to the sequential program or deleting one of the one or more macro tasks from the sequential program; and
assigning again the sequential program, to which addition or deletion of the macro task is carried out, to the plurality of cores under a condition that the one or more macro tasks previously assigned to the plurality of cores do not migrate among the plurality of cores,
wherein among the plurality of cores, a target core to which the new macro task is assigned is determined so that an execution duration of the segmented program after adding the new macro task has a minimum value compared with a case in which the new macro task is assigned to another core under a condition that the new macro task has no dependency relation with the one or more macro tasks included in the sequential program.

6. The parallelization compiler according to claim 5 , wherein,
when the new macro task is added to the sequential program, in compiling of the sequential program into the segmented program, an assignment of the one or more macro tasks to the plurality of cores is maintained without change and a target core to which the new macro task is assigned among the plurality of cores is determined based on an execution duration of the segmented program to which the new macro task is added.

7. The parallelization compiler according to claim 6 , wherein,
among the plurality of cores, the target core to which the new macro task is assigned is determined so that the execution duration of the segmented program after adding the new macro task has a minimum value compared with a case in which the new macro task is assigned to another core.

8. The parallelization compiler according to claim 5 , wherein,
when the one of the one or more macro tasks is to be deleted from the sequential program, in compiling of the sequential program into the segmented program, a deletion of the one of the one or more macro tasks is carried out and an assignment of the remains of the one or more macro tasks to the plurality of cores is maintained without change.

9. The parallelization compiler according to claim 8 , wherein,
when deleting the one of the one or more macro tasks from the sequential program, information indicating a data dependency related to the one of the one or more macro tasks is remained without deletion.

10. A vehicular device comprising:
a multi-core processor, wherein
the multi-core processor operates based on a segmented program, which is executable by the multi-core processor and is generated by parallelization from a sequential program executable by a single-core processor, and
the multi-core processor is configured to:
assign one or more macro tasks included in the sequential program to a plurality of cores included in the multi-core processor in order to generate the segmented program;
add a new macro task to the sequential program or deleting one of the one or more macro tasks from the sequential program; and
assign again the sequential program, to which addition or deletion of the macro task is carried out, to the plurality of cores under a condition that the one or more macro tasks previously assigned to the plurality of cores do not migrate among the plurality of cores,
wherein among the plurality of cores, a target core to which the new macro task is assigned is determined so that an execution duration of the segmented program after adding the new macro task has a minimum value compared with a case in which the new macro task is assigned to another core under a condition that the new macro task has no dependency relation with the one or more macro tasks included in the sequential program.

11. The vehicular device according to claim 10 , wherein,
when the new macro task is added to the sequential program, in compiling of the sequential program into the segmented program, an assignment of the one or more macro tasks to the plurality of cores is maintained without change and a target core to which the new macro task is assigned among the plurality of cores is determined based on an execution duration of the segmented program to which the new macro task is added.

12. The vehicular device according to claim 11 , wherein,
among the plurality of cores, the target core to which the new macro task is assigned is determined so that the execution duration of the segmented program after adding the new macro task has a minimum value compared with a case in which the new macro task is assigned to another core.

13. The vehicular dev

Assignees

• Denso Corp
• Univ Waseda

Inventors

• Nobuta Kazushi
• Suzuki Noriyuki
• Kasahara Hironori
• Kimura Keiji
• Mikami Hiroki
• Umeda Dan

Classifications

• G06F8/451 Primary

  Code distribution (considering CPU load at run-time G06F9/505; load rebalancing G06F9/5083) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title