Balancing allocated cache pages among storage devices in a flash cache

Patent metadata

Field	Value
Publication number	US-9933952-B1
Application number	US-201615086527-A
Country	US
Kind code	B1
Filing date	Mar 31, 2016
Priority date	Mar 31, 2016
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

Described herein are techniques for use in balancing allocated cache pages among storage devices in a flash cache. The techniques comprise determining an expected number of allocated cache pages in connection with a non-volatile storage device that forms at least part of a flash cache. The techniques also comprise performing a comparison between the expected number of allocated cache pages and an actual number of allocated or free cache pages in connection with the non-volatile storage device. The techniques further comprise selecting, based on the comparison, a free cache page in connection with the non-volatile storage device to allocate as a cache page.

First claim

What is claimed is:

1. A computer-implemented method, comprising:
determining an expected number of allocated cache pages in connection with a non-volatile storage device that forms at least part of a flash cache;
performing a comparison between the expected number of allocated cache pages and an actual number of allocated or free cache pages in connection with the non-volatile storage device; and
based on the comparison, selecting a free cache page in connection with the non-volatile storage device to allocate as a cache page, to balance the allocated or free cache pages among a plurality of non-volatile storage devices that form the flash cache, wherein the non-volatile storage device is one of the plurality of non-volatile storage devices that forms the flash cache; and wherein determining the expected number of allocated cache pages in connection with the non-volatile storage device comprises: forming a first value relating to available cache storage associated with the non-volatile storage device; forming a second value relating to available cache storage associated with the flash cache; forming a ratio of the first value to the second value to produce a third value; forming a fourth value relating to an actual number of allocated cache pages in connection with the flash cache; and forming a product of the third and fourth values to produce the expected number of allocated cache pages in connection with the non-volatile storage device.

2. The method as claimed in claim 1 , wherein the non-volatile storage device is one of the plurality of non-volatile storage devices that forms the flash cache; and
wherein the method further comprises:
receiving a write I/O relating to a cache page in connection with another non-volatile storage device of the plurality of non-volatile storage devices that forms the flash cache;
performing a second comparison between the expected number of allocated cache pages and an actual number of allocated or free cache pages in connection with the another non-volatile storage device;
based on the second comparison, writing data associated with the write I/O to the selected cache page in connection with the non-volatile storage device; and
sending a command to free the cache page in connection with the another non-volatile storage device.

3. The method as claimed in claim 1 , wherein the non-volatile storage device is one of the plurality of non-volatile storage devices that forms the flash cache; and
wherein the method further comprises:
receiving data that is one of promoted or demoted to the flash cache; and
storing the data in the selected cache page in connection with the non-volatile storage device of the plurality of non-volatile storage devices that forms the flash cache.

4. The method as claimed in claim 1 , wherein the non-volatile storage device is one of the plurality of non-volatile storage devices that forms the flash cache; and
wherein the method further comprises:
detecting an intention to remove one of the plurality of non-volatile storage devices from the flash cache; and
moving data associated with a cache page in connection with the one of the plurality of non-volatile storage devices to the selected cache page.

5. The method as claimed in claim 1 , wherein the actual number corresponds to the amount of allocated cache pages in connection with the non-volatile storage device; and
wherein performing the comparison, comprises:
determining if the expected number of allocated cache pages is greater or less than the actual number of allocated cache pages in connection with the non-volatile storage device; and
in response to determining the expected number is greater than the actual number, determining to select a free cache page in connection with the non-volatile storage device to allocate as a cache page.

6. The method as claimed in claim 1 , wherein the actual number corresponds to the amount of free cache pages in connection with the non-volatile storage device; and
wherein performing the comparison, comprises:
determining if the expected number of allocated cache pages is greater or less than the actual number of free cache pages in connection with the non-volatile storage device; and
in response to determining the expected number is less than the actual number, determining to select a free cache page in connection with the non-volatile storage device to allocate as a cache page.

7. An apparatus, comprising:
memory; and
processing circuitry coupled to the memory, the memory storing program code which, when executed by the processing circuitry, cause the processing circuitry to:
determine an expected number of allocated cache pages in connection with a non-volatile storage device that forms at least part of a flash cache;
perform a comparison between the expected number of allocated cache pages and an actual number of allocated or free cache pages in connection with the non-volatile storage device; and
based on the comparison, select a free cache page in connection with the non-volatile storage device to allocate as a cache page, to balance the allocated or free cache pages among a plurality of non-volatile storage devices that form the flash cache, wherein the non-volatile storage device is one of the plurality of non-volatile storage devices that forms the flash cache; and wherein determining the expected number of allocated cache pages in connection with the non-volatile storage device comprises: forming a first value relating to available cache storage associated with the non-volatile storage device; forming a second value relating to available cache storage associated with the flash cache; forming a ratio of the first value to the second value to produce a third value; forming a fourth value relating to an actual number of allocated cache pages in connection with the flash cache; and forming a product of the third and fourth values to produce the expected number of allocated cache pages in connection with the non-volatile storage device.

8. The apparatus as claimed in claim 7 , wherein the non-volatile storage device is one of the plurality of non-volatile storage devices that forms the flash cache; and
wherein the memory stores program code which, when executed by the processing circuitry, cause the processing circuitry to:
receive a write I/O relating to a cache page in connection with another non-volatile storage device of the plurality of non-volatile storage devices that forms the flash cache;
perform a second comparison between the expected number of allocated cache pages and an actual number of allocated or free cache pages in connection with the another non-volatile storage device;
based on the second comparison, write data associated with the write I/O to the selected cache page in connection with the non-volatile storage device; and
send a command to free the cache page in connection with the another non-volatile storage device.

9. The apparatus as claimed in claim 7 , wherein the non-volatile storage device is one of the plurality of non-volatile storage devices that forms the flash cache; and
wherein the memory stores program code which, when executed by the processing circuitry, cause the processing circuitry to:
receive data that is one of promoted or demoted to the flash cache; and
store the data in the selected cache page in connection with the non-volatile storage device of the plurality of non-volatile storage devices that forms the flash cache.

10. The apparatus as claimed in claim 7 , wherein the non-volatile storage device is one of the plurality of non-volatile storage devices that forms the flash cache; and
wherein the memory stores program code which, when executed by the processing circuitry, ca

Assignees

• Emc Corp
• Emc Ip Holding Co Llc

Inventors

• Li Liam Xiongcheng
• Xu Xinlei
• Yang Lifeng
• Gao Jian
• Chen Lili

Classifications

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/214

  Solid state disk · CPC title

• G06F3/0689 Primary

  Disk arrays, e.g. RAID, JBOD · CPC title

• G06F12/0871

  Allocation or management of cache space · CPC title

• G06F2212/7205

  Cleaning, compaction, garbage collection, erase control · CPC title