Through wiring substrate

Patent metadata

Field	Value
Publication number	US-9930779-B2
Application number	US-201715581606-A
Country	US
Kind code	B2
Filing date	Apr 28, 2017
Priority date	Apr 28, 2016
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

A through wiring substrate comprises a substrate having a pair of principal surfaces and a through hole penetrating between the pair of principal surfaces, the pair of principal surfaces and an inner surface of the through hole being electrically insulative; a through electrode provided on the inner surface of the through hole; a first wiring layer provided on one of the principal surfaces and connected to the through electrode; a second wiring layer provided on the other of the principal surfaces and connected to the through electrode; an underlying metal layer provided between the one of the principal surfaces and the first wiring layer; and catalyst metal particles existing between the underlying metal layer and the first wiring layer and between the through electrode and the inner surface of the through hole.

First claim

What is claimed is:

1. A through wiring substrate comprising:
a substrate having a pair of principal surfaces and a through hole penetrating between the pair of principal surfaces, the pair of principal surfaces and an inner surface of the through hole being electrically insulative;
a through electrode provided on the inner surface of the through hole;
a first wiring layer provided on one of the principal surfaces and connected to the through electrode;
a second wiring layer provided on the other of the principal surfaces and connected to the through electrode;
an underlying metal layer provided between the one of the principal surfaces and the first wiring layer, the underlying metal layer having a first underlying metal layer containing at least one selected from the group consisting of Cr, Ni, W, Ta and Ti and a second underlying metal layer containing at least one selected from the group consisting of Cu and Al on the first underlying metal layer; and
catalyst metal particles existing between the underlying metal layer and the first wiring layer and between the through electrode and the inner surface of the through hole, the second underlying metal layer being between the first underlying metal layer and the catalyst metal particles.

2. The through wiring substrate according to claim 1 , wherein the catalyst metal particles are particles containing a noble metal.

3. The through wiring substrate according to claim 1 , further comprising a nonelectrolytic plating layer covering the first wiring layer.

4. The through wiring substrate according to claim 1 , comprising a plurality of wiring structures each including the first wiring layer, the underlying metal layer and the catalyst metal particles on the one of the principal surfaces, a gap provided between the wiring structures.

5. The through wiring substrate according to claim 1 , further comprising
the underlying metal layer between the other of the principal surfaces and the second wiring layer, wherein
the catalyst metal particles further exist between the underlying metal layer and the second wiring layer.

6. The through wiring substrate according to claim 1 , wherein the first and the second underlying metal layers are of different metals.

7. The through wiring substrate according to claim 1 , wherein the second underlying metal layer is thicker than the first underlying metal layer.

Assignees

• Tdk Corp

Inventors

• Yoshida Kenichi
• Harada Tatsuya

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/698

  Semiconductor materials that are electrically insulating, e.g. undoped silicon · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title