Thermal metal ground for integrated circuit resistors

Patent metadata

Field	Value
Publication number	US-9930769-B2
Application number	US-201414181187-A
Country	US
Kind code	B2
Filing date	Feb 14, 2014
Priority date	Feb 14, 2014
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

Metal thermal grounds are used for dissipating heat from integrated-circuit resistors. The resistors may be formed using a front end of line layer, for example, a titanium-nitride layer. A metal region (e.g., in a first metal layer) is located over the resistors to form a heat sink. An area of thermal posts connected to the metal region is also located over the resistor. The metal region can be connected to the substrate of the integrated circuit to provide a low impedance thermal path out of the integrated circuit.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a first resistor;
a second resistor;
a metal region disposed parallel to and overlapping at least parts of the first and second resistors, wherein the metal region is thermally connected to a substrate of the integrated circuit via first, second, and third sets of contacts, wherein the second set of contacts is situated between the first and second resistors, wherein the first resistor is situated between the first and second sets of contacts, and wherein the second resistor is situated between the second and third sets of contacts;
a first two-dimensional array of thermal posts electrically connected to the metal region and disposed between the metal region and overlapping the first resistor, the first two-dimensional array of thermal posts electrically isolated from the first resistor; and
a second two-dimensional array of thermal posts electrically connected to the metal region and disposed between the metal region and overlapping the second resistor, the second two-dimensional array of thermal posts electrically isolated from the second resistor, wherein rows of the first two-dimensional array of thermal posts are aligned with rows of the second two-dimensional array of thermal posts, and wherein the first, second, and third sets of contacts comprise first, second, and third one-dimensional array of contacts, wherein the one-dimensional array of contacts are aligned with the rows of the first and second two-dimensional arrays of thermal posts;
first and second sets of resistor contacts electrically coupled to the first resistor; and
third and fourth sets of resistor contacts electrically coupled to the second resistor, wherein the first and second sets of resistor contacts comprise first and second one-dimensional arrays of resistor contacts, wherein the resistor contacts of the first and second one-dimensional arrays are aligned with columns of the first two-dimensional array of thermal posts, wherein the third and fourth sets of resistor contacts comprise third and fourth one-dimensional arrays of resistor contacts, wherein the resistor contacts of the third and fourth one-dimensional arrays are aligned with columns of the second two-dimensional array of thermal posts.

2. The integrated circuit of claim 1 , wherein the first and second resistors are formed of titanium nitride.

3. The integrated circuit of claim 1 , wherein the metal region is formed in a lowest metal layer of the integrated circuit.

4. The integrated circuit of claim 1 , wherein the metal region is disposed above the first and second resistors.

5. The integrated circuit of claim 1 wherein the first and second resistors are surrounded by a dielectric.

6. A method for dissipating heat from first and second resistors in an integrated circuit, the method comprising:
providing a metal region disposed parallel to and overlapping at least parts of the first and second resistors;
conducting heat from the first resistor to the metal region using a first two-dimensional array of thermal posts disposed between the metal region and the first resistor, the first two-dimensional array of thermal posts electrically isolated from the first resistor;
conducting heat from the second resistor to the metal region using a second two-dimensional array of thermal posts disposed between the metal region and the second resistor, the second two-dimensional array of thermal posts electrically isolated from the second resistor, wherein rows of the first two-dimensional array of thermal posts are aligned with rows of the second two-dimensional array of thermal posts;
conducting heat from the metal region to a substrate via first, second, and third sets of contacts, wherein the second set of contacts is situated between the first and second resistors, wherein the first resistor is situated between the first and second sets of contacts, and wherein the second resistor is situated between the second and third sets of contacts, wherein the first, second, and third sets of contacts comprise first, second, and third one-dimensional array of contacts, wherein the one-dimensional array of contacts are aligned with the rows of the first and second two-dimensional arrays of thermal posts;
connecting the first resistor to circuitry via first and second sets of resistor contacts electrically coupled to the first resistor; and
connecting the second resistor to circuitry via third and fourth sets of resistor contacts electrically coupled to the second resistor, wherein the first and second sets of resistor contacts comprise first and second one-dimensional arrays of resistor contacts, wherein the resistor contacts of the first and second one-dimensional arrays are aligned with columns of the first two-dimensional array of thermal posts, wherein the third and fourth sets of resistor contacts comprise third and fourth one-dimensional arrays of resistor contacts, wherein the resistor contacts of the third and fourth one-dimensional arrays are aligned with columns of the second two-dimensional array of thermal posts.

7. The method of claim 6 , wherein the first and second two-dimensional arrays of thermal posts are electrically connected to the metal region.

8. The method of claim 6 , wherein the metal region is electrically connected to the substrate of the integrated circuit.

9. The method of claim 6 , wherein the first and second resistors are formed of titanium nitride.

10. The method of claim 6 , wherein the metal region is formed in a metal layer closest to the substrate of the integrated circuit.

11. The method of claim 6 , wherein the first and second resistors are surrounded by a dielectric.

12. An integrated circuit, comprising:
a first resistor;
a second resistor;
a metal region disposed parallel to and overlapping at least parts of the first and second resistors;
means for conducting heat from the first resistor to the metal region, wherein the means for conducting heat includes a first two-dimensional array of thermal posts disposed between the metal region and the first resistor, the first two-dimensional array of thermal posts electrically isolated from the first resistor;
means for conducting heat from the second resistor to the metal region, wherein the means for conducting heat includes a second two-dimensional array of thermal posts disposed between the metal region and the second resistor, the second two-dimensional array of thermal posts electrically isolated from the second resistor, wherein rows of the first two-dimensional array of thermal posts are aligned with rows of the second two-dimensional array of thermal posts;
first, second, and third means for thermally connecting the metal region to a substrate, wherein the second thermally connecting means is situated between the first and second resistors, wherein the first resistor is situated between the first and second thermally connecting means, and wherein the second resistor is situated between the second and third thermally connecting means, wherein the first, second, and third thermally connecting means comprise first, second, and third one-dimensional array of contacts, wherein the one-dimensional array of contacts are aligned with the rows of the first and second two-dimensional arrays of thermal posts;
means for electrically connecting circuitry to the first resistor including first and second sets of resistor contacts electrically coupled to the first resistor; and
means for electrically connecting circuitry to the second resistor including third and fourth sets of resistor contacts electrically coupled to the second resistor, wherein the first and second sets of resistor contacts comprise first and

Assignees

• Qualcomm Inc

Inventors

• Mittal Arpit
• Loke Alvin Leng Sun
• Saeidi Mehdi
• Drennan Patrick

Classifications

• H10W40/228 Primary

  the projecting parts being wire-shaped or pin-shaped · CPC title

• H10W40/22

  characterised by their shape, e.g. having conical or cylindrical projections · CPC title

• H10W20/498

  Resistive arrangements or effects of, or between, wiring layers · CPC title

• H01C1/01

  Mounting; Supporting · CPC title

• H05K1/0204 Primary

  using means for thermal conduction connection in the thickness direction of the substrate (H05K1/0207 takes precedence) · CPC title