Preservation of a TTL parameter in a network element

Patent metadata

Field	Value
Publication number	US-9929966-B2
Application number	US-201514590826-A
Country	US
Kind code	B2
Filing date	Jan 6, 2015
Priority date	Mar 21, 2014
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

In a system having multiple internal Internet protocol (IP) stacks, such as a network element, a value of a time-to-live (TTL) parameter may not be changed by an ingress IP stack. An indication of internal forwarding within the system may be used. An egress IP stack may decrement the value of the TTL parameter. A public network address for the system may be used for response packets to diagnostic packets received by the system.

First claim

What is claimed is:

1. A method for preserving time-to-live (TTL) parameters in systems having multiple internal Internet protocol (IP) stacks, the method comprising:
receiving an trace route packet at an ingress IP stack in a system executing a plurality of IP stacks, including the ingress IP stack;
based upon destination information in the trace route packet, determining a subsequent IP stack included in the plurality of IP stacks to forward the trace route packet to;
responsive to determining the subsequent IP stack, setting an indication of internal routing in the trace route packet, wherein a value of a TTL parameter in the trace route packet is not changed by the ingress IP stack;
generating a response packet to the trace route packet, wherein a public IP address for the network element is used as source information in the response packet;
forwarding the trace route packet, including the indication of internal routing, to the subsequent IP stack;
when the subsequent IP stack is an egress IP stack in the system:
clearing the indication of internal routing in the trace route packet;
decrementing the value of the TTL parameter in the trace route packet; and
forwarding the trace route packet to a destination external to the system.

2. The method of claim 1 , wherein determining the subsequent IP stack includes:
performing a route lookup for the trace route packet based on destination information included in the trace route packet.

3. The method of claim 1 , wherein the system is a network element.

4. The method of claim 3 , wherein the ingress IP stack is executed by a network element processor and the subsequent IP stack is executed by a network interface processor.

5. The method of claim 3 , wherein the ingress IP stack is executed by a first network interface processor and the subsequent IP stack is executed by a second network interface processor.

6. A network element for preserving time-to-live (TTL) parameters and having multiple internal Internet protocol (IP) stacks, the network element comprising:
a first processor having access to a first memory media storing first instructions executable by the first processor;
a second processor having access to a second memory media storing second instructions executable by the second processor;
a first network port accessible to the first processor;
a second network port accessible to the second processor; and
an internal network accessible to the first processor and to the second processor,
wherein the first instructions are executable by the first processor to implement an ingress IP stack, the first instructions further executable by the first processor to:
receive a trace route packet at the first network port;
based upon destination information in the trace route packet, determine that the trace route packet is to be forwarded to the second processor via the internal network;
responsive to determining that the trace route packet is to be forwarded via the internal network, set an indication of internal routing in the trace route packet, wherein a value of a TTL parameter in the trace route packet is not changed;
generate a response packet to the trace route packet, wherein a public IP address for the network element is used as source information in the response packet; and
forward the trace route packet, including the indication of internal routing, to the second processor,

wherein the second instructions are executable by the second processor to implement a subsequent IP stack, the second instructions further executable by the second processor to:
receive the trace route packet; and
when the subsequent IP stack is an egress IP stack in the network element for the trace route packet:
clear the indication of internal routing in the trace route packet;
decrement the value of the TTL parameter in the trace route packet; and
forward the trace route packet at the second network port to a destination external to the network element.

7. The network element of claim 6 , wherein the first instructions to determine that the trace route packet is to be forwarded to the second processor via the internal network include first instructions to:
perform a route lookup for the trace route packet based on destination information included in the trace route packet.

8. The network element of claim 6 , wherein the first processor is a network element processor and the second processor is a network interface processor.

9. The network element of claim 6 , wherein the first processor is a first network interface processor and the second processor is a second network interface processor.

10. The network element of claim 6 , wherein the second processor is a network element processor and the first processor is a network interface processor.

11. A network including a network element for preserving time-to-live (TTL) parameters and having multiple internal Internet protocol (IP) stacks, the network element comprising:
a first processor having access to a first memory media storing first instructions executable by the first processor;
a second processor having access to a second memory media storing second instructions executable by the second processor;
a first network port accessible to the first processor;
a second network port accessible to the second processor; and
an internal network accessible to the first processor and to the second processor,
wherein the first instructions are executable by the first processor to implement an ingress IP stack, the first instructions further executable by the first processor to:
receive a trace route packet at the first network port;
based upon destination information in the trace route packet, determine that the trace route packet is to be forwarded to the second processor via the internal network;
responsive to determining that the trace route packet is to be forwarded via the internal network, set an indication of internal routing in the trace route packet, wherein a value of a TTL parameter in the trace route packet is not changed;
generate a response packet to the trace route packet, wherein a public IP address for the network element is used as source information in the response packet; and
forward the trace route packet, including the indication of internal routing, to the second processor,

wherein the second instructions are executable by the second processor to implement a subsequent IP stack, the second instructions further executable by the second processor to:
receive the trace route packet; and
when the subsequent IP stack is an egress IP stack in the network element for the trace route packet:
clear the indication of internal routing in the trace route packet;
decrement the value of the TTL parameter in the trace route packet; and
forward the trace route packet at the second network port to a destination external to the network element.

12. The network of claim 11 , wherein the first instructions to determine that the trace route packet is to be forwarded to the second processor via the internal network include first instructions to:
perform a route lookup for the trace route packet based on destination information included in the trace route packet.

13. The network of claim 11 , wherein the first processor is a network element processor and the second processor is a network interface processor.

14. The network of claim 11 , wherein the first processor is a first network interface processor and the second processor is a second network interface processor.

15. The network of claim 11 , wherein the second processor is a network element processor and the first process

Assignees

• Nakakes Tintooda
• Smith Albert V
• Amanullah Nasir Iqbal
• Nguyen Joseph
• Sun Xinxin
• Fujitsu Ltd

Inventors

• Nakakes Tintooda
• Smith Albert V
• Amanullah Nasir Iqbal
• Nguyen Joseph
• Sun Xinxin

Classifications

• H04L45/26

  Route discovery packet · CPC title

• H04L69/161 Primary

  Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields · CPC title

• H04L47/34

  ensuring sequence integrity, e.g. using sequence numbers · CPC title

• H04L47/286 Primary

  Time to live · CPC title