Next packet protection for communications in overlapping frequencies

Patent metadata

Field	Value
Publication number	US-9929753-B1
Application number	US-201615385807-A
Country	US
Kind code	B1
Filing date	Dec 20, 2016
Priority date	Oct 11, 2016
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

Techniques for harmonizing wireless communications performed by a computing device which communicates using varying wireless communication standards are described herein. For instance, a computing device may include multiple chipsets with associated antennas that are configured to perform wireless communications using separate wireless standards which operate at overlapping frequencies. To avoid performance degradation experienced in simultaneous use cases with communications operating at overlapping frequencies, the multiple chipsets may be configured with logic to determine which communications are prioritized when multiple chipsets attempt to communicate simultaneously. The multiple chipsets may be communicatively coupled to coordinate their communications by prioritizing certain types of communications over other types of communications to avoid simultaneous communications in overlapping frequencies. In this way, multiple chipsets that communicate using different standards at overlapping frequencies may avoid performance issues experienced in simultaneous use cases, while performing the communications which are of a highest priority level.

First claim

What is claimed is:

1. A computing device comprising:
one or more processors;
one or more first antennas;
one or more second antennas;
a first chipset, compatible with a first communication standard, to communicate signals in a first frequency range using the one or more first antennas;
a second chipset, compatible with a second communication standard, to communicate signals in a second frequency range using the one or more second antennas, wherein the first frequency range and the second frequency range at least partially overlap;
a three-wire hardware interface electrically connecting the first chipset and the second chipset;
a coexistence management platform module encoded on the second chipset and comprising logic configured to perform acts comprising:
detecting a first portion of data of a first packet sent from a secondary device, the first packet conforming to the second communication standard;
based at least in part on detecting the first portion of data, placing a first logic high signal on a first wire of the three-wire hardware interface, the first logic high signal indicating a request to communicate;
determining, based on the first portion of data, that a destination device address of the first packet corresponds to a device address associated with the computing device;
based at least in part on determining that the destination device address corresponds to a device address associated with the computing device, placing a second logic high signal on a second wire of the three-wire hardware interface, the second logic high signal indicating the request to communicate is associated with receiving data from the secondary device, the secondary device communicating using the second communication standard;
detecting, via a third wire of the three-wire hardware interface, a third logic high signal allowing the second chipset to communicate; and
receiving the first packet.

2. The computing device as recited in claim 1 , the acts further comprising:
determining that a second portion of data of the first packet was corrupted or not received at the second chipset;
placing a first logic low signal on the second wire while the first logic high signal is maintained on the first wire;
detecting a first portion of data of a second packet, the second packet conforming to the second communication standard;
based at least in part on detecting the first portion of data of the second packet, placing a third logic high signal on the second wire;
detecting, via the third wire of the three-wire hardware interface, a fifth logic high signal allowing the second chipset to communicate; and
receiving the second packet.

3. The computing device as recited in claim 2 , the acts further comprising:
determining that second chipset has finished receiving data from the secondary device; and
based at least in part on determining that second chipset has finished receiving the data:
placing a second logic low signal on the first wire; and
placing a third logic low signal on the second wire.

4. A method comprising:
receiving, by a first antenna associated with a first chipset of a computing device, a first portion of a first packet sent from a communication device, wherein the first chipset is configured to communicate signals in a first frequency range using the first antenna;
determining that a destination device address included in the first portion of the first packet corresponds to a device address of the computing device;
at least in response to determining that the destination address corresponds to the device address of the computing device:
sending a first signal to a second chipset of the computing device indicating a request to communicate, wherein the second chipset is configured to communicate signals in a second frequency range using a second antenna, wherein the first frequency range and second frequency range at least partially overlap; and
sending a second signal to the second chipset indicating a type of communication associated with the request to communicate.

5. The method of claim 4 , wherein:
sending the first signal indicating the request to communicate comprises placing a first logic high signal on a first conductor of an interface connecting the first chipset and the second chipset; and
sending the second signal indicating the type of communication comprises placing a second logic high signal on a second conductor of the interface.

6. The method of claim 5 , further comprising:
determining that a second portion of the first packet was corrupted or not received; and
placing a first logic low signal on the second conductor while the first logic high signal is maintained on the first conductor.

7. The method of claim 6 , further comprising:
detecting a third portion of a second packet;
based at least in part on detecting the third portion of the second packet, placing a third logic high signal on the second conductor;
detecting, via a third conductor of the interface, a fourth logic high signal allowing the first chipset to communicate data; and
receiving, by the first chipset, the second packet.

8. The method of claim 6 , further comprising:
determining that the first chipset is finished communicating data in the first frequency range;
based at least in part on determining that the first chipset is finished communicating data in the first frequency range:
placing a second logic low signal on the first conductor; and
placing a third logic low signal on the second conductor.

9. The method of claim 4 , wherein receiving the first portion of the first packet sent from the communication device comprises:
detecting, by the first antenna, a signal communicated using an 802.15.4 technology standard, wherein the first chipset is configured to communicate signals at the first frequency range using the 802.15.4 technology standard.

10. The method of claim 4 , wherein sending the second signal to the second chipset indicating the type of communication comprises sending the second signal to the second chipset indicating the request to communicate comprises a request to receive data.

11. The method of claim 4 , further comprising:
receiving, from the second chipset, a third signal allowing the first chipset to communicate; and
receiving, by the first chipset, the first packet.

12. A computing device comprising:
one or more processors;
a first antenna;
a second antenna;
a first chipset to communicate signals in a first frequency range using the first antenna;
a second chipset to communicate signals in a second frequency range using the second antenna, wherein the first frequency range and the second frequency range at least partially overlap;
an interface electrically connecting the first chipset and the second chipset;
a coexistence management platform module encoded on the first chipset and comprising logic configured to, when executed by the one or more processors, perform acts comprising:
placing a first logic high signal on a first conductor of the interface, the first logic high signal indicating a request to communicate using a first communication protocol;
placing a first logic low signal on a second conductor of the interface, the first logic low signal indicating a type of communication associated with the first communication protocol;
detecting a second logic high signal on a third conductor of the interface allowing the first chipset to communicate using the first communication protocol;
sending, by the first chipset, one or more first packets to a communication device;
receiving, by the first chipset, one or more first acknowledgement packets from the communication device;
determining a device ty

Assignees

• Amazon Tech Inc

Inventors

• Hsu Morris Yuanhsiang
• Patel Pratik Kalpesh
• Gao Qinghai
• Kapur Ateet
• Jorgovanovic Milos
• Desai Jay Praful
• Guo Jin
• Shaw King

Classifications

• H04W72/566

  of the information or information source or recipient · CPC title

• H04W72/56

  based on priority criteria · CPC title

• H04W72/21

  in the uplink direction of a wireless link, i.e. towards the network · CPC title

• H04W72/23

  in the downlink direction of a wireless link, i.e. towards a terminal · CPC title

• H04W76/16

  Involving different core network technologies, e.g. a packet-switched [PS] bearer in combination with a circuit-switched [CS] bearer · CPC title