Distributed amplifiers with impedance compensation circuits

Patent metadata

Field	Value
Publication number	US-9929707-B1
Application number	US-201615384483-A
Country	US
Kind code	B1
Filing date	Dec 20, 2016
Priority date	Dec 20, 2016
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

An embodiment of a distributed amplifier includes an output collection line, a plurality of tap nodes distributed along the output collection line, and a plurality of amplification paths coupled to the tap nodes. An embodiment of an amplification path includes an amplifier and a compensation circuit. The amplifier is configured to receive and amplify an input RF signal to produce an amplified RF signal at an amplifier output. A compensation circuit input is electrically coupled to the amplifier output, and a compensation circuit output is electrically coupled to one of the tap nodes. The compensation circuit includes a series inductance electrically coupled between the compensation circuit input and the compensation circuit output, and a shunt capacitance electrically coupled between the series inductance and a ground reference node. The amplifiers and the compensation circuit may be monolithically implemented on a single substrate, or may be implemented on separate substrates.

First claim

What is claimed is:

1. A distributed amplifier comprising:
an output collection line that includes a plurality of output transmission line segments electrically coupled in series between a first end and a second end of the output collection line;
a plurality of tap nodes, wherein a different one of the tap nodes is located at an input end of each of the plurality of output transmission line segments; and
a plurality of amplification paths, wherein each of the amplification paths is electrically coupled to a different one of the tap nodes, and each of the amplification paths includes
an amplifier with an amplifier input and an amplifier output, wherein the amplifier is configured to receive an input RF signal at the amplifier input, and to amplify the input RF signal to produce an amplified RF signal at the amplifier output, and
a compensation circuit with a compensation circuit input and a compensation circuit output, wherein the compensation circuit input is electrically coupled to the amplifier output, the compensation circuit output is electrically coupled to one of the tap nodes, and the compensation circuit includes a series inductance with a first terminal electrically coupled to the compensation circuit input and a second terminal electrically coupled to the compensation circuit output, and a shunt capacitance electrically coupled between the second terminal of the series inductance and a ground reference node, wherein the series inductance has a non-negligible inductance value, and the series inductance and the shunt capacitance form a first low pass circuit.

2. The distributed amplifier of claim 1 , wherein each amplifier includes a power transistor with a control terminal corresponding to the amplifier input, and a current conducting terminal corresponding to the amplifier output, and the distributed amplifier further comprises:
a semiconductor die, wherein the power transistor is monolithically formed with the semiconductor die, and wherein the series inductance and the shunt capacitance are physically coupled to the semiconductor die.

3. The distributed amplifier of claim 2 , wherein the semiconductor die comprises a semiconductor substrate formed from a high resistivity semiconductor material with a bulk resistivity of at least 1000 ohm/centimeter, and wherein the semiconductor substrate is selected from silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), gallium arsenide (GaAs), gallium nitride (GaN), GaN on silicon carbide, and GaN on silicon.

4. The distributed amplifier of claim 2 , wherein:
the semiconductor die comprises first and second conductive pads exposed at a surface of the semiconductor die;
the first conductive pad is electrically coupled to the first current conducting terminal;
the second conductive pad is electrically coupled to the compensation circuit output; and
the series inductance comprises a discrete inductor device with a first terminal connected to the first conductive pad, and a second terminal connected to the second conductive pad.

5. The distributed amplifier of claim 4 , wherein:
the semiconductor die further comprises a third conductive pad exposed at a surface of the semiconductor die; and
the series inductance further comprises a plurality of bondwires electrically coupled between the third conductive pad and one of the first or second conductive pads so that the series inductance includes a series combination of a first inductance formed from the discrete inductor device and a second inductance formed from the plurality of bondwires.

6. The distributed amplifier of claim 4 , wherein:
the semiconductor die comprises first and second conductive layers formed over a surface of a semiconductor substrate;
the shunt capacitance comprises an area capacitor formed from a portion of the first conductive layer, a portion of the second conductive layer, and dielectric material between the portions of the first and second conductive layers;
the portion of the first conductive layer is electrically coupled to the series inductance; and
the portion of the second conductive layer is electrically coupled to the ground reference node.

7. The distributed amplifier of claim 4 , wherein:
the semiconductor die further comprises a third conductive pad exposed at a surface of the semiconductor die and electrically coupled to the ground reference node; and
the shunt capacitance comprises a discrete capacitor device with a first terminal connected to the third conductive pad and a second terminal electrically coupled to the second conductive pad.

8. The distributed amplifier of claim 2 , wherein the output collection line is monolithically formed with the semiconductor die.

9. The distributed amplifier of claim 1 , wherein each amplifier includes a power transistor with a control terminal corresponding to the amplifier input, and a current conducting terminal corresponding to the amplifier output, and the distributed amplifier further comprises:
a semiconductor die, wherein the power transistor is monolithically formed with the semiconductor die; and
a separate substrate from the semiconductor die, wherein the shunt capacitance is physically coupled to the separate substrate, and the series inductance comprises a plurality of bondwires coupled between the semiconductor die and the separate substrate.

10. The distributed amplifier of claim 9 , wherein:
the separate die comprises first and second conductive pads exposed at a surface of the separate die;
the first conductive pad is electrically coupled to the plurality of bondwires;
the second conductive pad is electrically coupled to the compensation circuit output; and
the series inductance further comprises a discrete inductor device with a first terminal electrically coupled to the first conductive pad, and a second terminal electrically coupled to the second conductive pad so that the series inductance includes a series combination of a first inductance formed from the discrete inductor device and a second inductance formed from the plurality of bondwires.

11. The distributed amplifier of claim 9 , wherein the shunt capacitance comprises one or more capacitances selected from an integrated area capacitor and a discrete capacitor device connected to conductive pads exposed at a surface of the separate die.

12. The distributed amplifier of claim 9 , wherein the output collection line is physically coupled to the separate substrate.

13. The distributed amplifier of claim 1 , wherein the compensation circuit further comprises at least one additional low pass circuit coupled in series with the first low pass circuit.

14. The distributed amplifier of claim 1 , further comprising:
an input transmission line that includes a plurality of input transmission line segments electrically coupled in series between a first end and a second end of the input transmission line; and
a plurality of feeding nodes, wherein a different one of the feeding nodes is located at an output end of each of the plurality of input transmission line segments, and the amplifier input of each of the amplification paths is electrically coupled to a different one of the feeding nodes.

15. The distributed amplifier of claim 14 , wherein each amplifier includes a power transistor with a control terminal corresponding to the amplifier input, and a current conducting terminal corresponding to the amplifier output, and the distributed amplifier further comprises:
a semiconductor die, wherein the power transistor for each amplifier and the input transmission line are monolithically formed with the semiconductor die.

16.

Assignees

• Nxp Usa Inc

Inventors

• Frei Jeffrey Alois

Classifications

• H10W44/206

  Wires · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F2200/225

  the input circuit of an amplifying stage comprising an LC-network · CPC title

• H03F3/213

  in integrated circuits · CPC title