Semiconductor device and method for producing a semiconductor device

Patent metadata

Field	Value
Publication number	US-9929341-B2
Application number	US-201715489108-A
Country	US
Kind code	B2
Filing date	Apr 17, 2017
Priority date	Oct 3, 2013
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

A semiconductor device includes first pillar-shaped semiconductor layers, a first gate insulating film formed around the first pillar-shaped semiconductor layers, gate electrodes formed around the first gate insulating film, gate lines connected to the gate electrodes, a second gate insulating film formed around upper portions of the first pillar-shaped semiconductor layers, first contacts formed of a first metal material and formed around the second gate insulating film, second contacts formed of a second metal material and connecting upper portions of the first contacts and upper portions of the first pillar-shaped semiconductor layers, diffusion layers formed in lower portions of the first pillar-shaped semiconductor layers, pillar-shaped insulator layers formed on the second contacts, variable-resistance films formed around upper portions of the pillar-shaped insulator layers, and lower electrodes formed around lower portions of the pillar-shaped insulator layers and connected to the variable-resistance films.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a first pillar-shaped semiconductor layer,
a first gate insulating film formed around said first pillar-shaped semiconductor layer,
a gate electrode formed of metal and formed around said first gate insulating film,
a gate line formed of metal and connected to said gate electrode,
a second gate insulating film formed around an upper portion of said first pillar-shaped semiconductor layer,
a first contact formed of a first metal material and formed around said second gate insulating film,
a second contact formed of a second metal material and connecting an upper portion of said first contact and an upper portion of said first pillar-shaped semiconductor layer,
a diffusion layer formed in a lower portion of said first pillar-shaped semiconductor layer,
a pillar-shaped insulator layer formed on said second contact,
a variable-resistance film formed around an upper portion of said pillar-shaped insulator layer, and
a lower electrode formed around a lower portion of said pillar-shaped insulator layer and connected to said variable-resistance film.

2. The semiconductor device according to claim 1 , wherein said pillar-shaped insulator layer is a nitride film and said lower electrode is formed between said pillar-shaped insulator layer and said second contact.

3. The semiconductor device according to claim 1 , wherein said first metal material forming said first contact has a work function of 4.0 to 4.2 eV.

4. The semiconductor device according to claim 1 , wherein said first metal material forming said first contact has a work function of 5.0 to 5.2 eV.

5. The semiconductor device according to claim 1 , comprising:
a fin-shaped semiconductor layer formed on a semiconductor substrate so as to extend in one direction,
a first insulating film formed around said fin-shaped semiconductor layer,
said first pillar-shaped semiconductor layer formed on said fin-shaped semiconductor layer, and
said first gate insulating film formed around and below said gate electrode and said gate line,
wherein said gate line extends in a direction orthogonal to said fin-shaped semiconductor layer, and
said diffusion layer is formed in said fin-shaped semiconductor layer.

6. The semiconductor device according to claim 5 , wherein said diffusion layer formed in said fin-shaped semiconductor layer is further formed in said semiconductor substrate.

7. The semiconductor device according to claim 5 , further comprising a contact line extending parallel with said gate line and connected to said diffusion layer.

8. The semiconductor device according to claim 7 , comprising:
said fin-shaped semiconductor layer formed on said semiconductor substrate,
said first insulating film formed around said fin-shaped semiconductor layer,
a second pillar-shaped semiconductor layer formed on said fin-shaped semiconductor layer,
a contact electrode formed of metal and formed around said second pillar-shaped semiconductor layer,
said contact line formed of metal, extending in a direction orthogonal to said fin-shaped semiconductor layer, and connected to said contact electrode, and
said diffusion layer formed in said fin-shaped semiconductor layer and in a lower portion of said second pillar-shaped semiconductor layer,
wherein said contact electrode is connected to said diffusion layer.

9. The semiconductor device according to claim 8 , wherein a portion of said first gate insulating film is formed between said second pillar-shaped semiconductor layer and said contact electrode.

10. The semiconductor device according to claim 9 , wherein a portion of said first gate insulating film is formed around said contact electrode and around said contact line.

11. The semiconductor device according to claim 8 , wherein a linewidth of said second pillar-shaped semiconductor layer in the direction orthogonal to said fin-shaped semiconductor layer is equal to a linewidth of said fin-shaped semiconductor layer in a direction orthogonal to a direction in which said fin-shaped semiconductor layer extends.

12. The semiconductor device according to claim 8 , wherein an outer linewidth of said contact electrode is equal to a linewidth of said contact line.

13. The semiconductor device according to claim 5 , wherein an outer linewidth of said gate electrode is equal to a linewidth of said gate line, and
a linewidth of said first pillar-shaped semiconductor layer in said direction orthogonal to said fin-shaped semiconductor layer is equal to a linewidth of said fin-shaped semiconductor layer in the direction orthogonal to said fin-shaped semiconductor layer.

14. The semiconductor device according to claim 1 , comprising:
said first pillar-shaped semiconductor layer formed on a semiconductor substrate, and
said first gate insulating film formed around and below said gate electrode and said gate line,
wherein said diffusion layer is formed in said semiconductor substrate.

15. The semiconductor device according to claim 14 , further comprising a contact line extending parallel with said gate line and connected to said diffusion layer.

16. The semiconductor device according to claim 14 , further comprising:
a second pillar-shaped semiconductor layer formed on said semiconductor substrate,
a contact electrode formed of metal and formed around said second pillar-shaped semiconductor layer,
a contact line connected to said contact electrode, and
said diffusion layer formed in a lower portion of said second pillar-shaped semiconductor layer,
wherein said contact electrode is connected to said diffusion layer.

17. The semiconductor device according to claim 16 , wherein a portion of said first gate insulating film is formed between said second pillar-shaped semiconductor layer and said contact electrode.

18. The semiconductor device according to claim 17 , wherein a portion of said first gate insulating film is formed around said contact electrode and around said contact line.

19. The semiconductor device according to claim 16 , wherein an outer linewidth of said contact electrode is equal to a linewidth of said contact line.

20. The semiconductor device according to claim 14 , wherein an outer linewidth of said gate electrode is equal to a linewidth of said gate line.

21. A method for producing a semiconductor device, the method comprising:
a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer,
a second step, following the first step, of forming a first pillar-shaped semiconductor layer, a first dummy gate derived from a first polysilicon, a second pillar-shaped semiconductor layer, and a second dummy gate derived from the first polysilicon,
a third step, following the second step, of forming a third dummy gate and a fourth dummy gate on side walls of the first dummy gate, the first pillar-shaped semiconductor layer, the second dummy gate, and the second pillar-shaped semiconductor layer,
a fourth step, following the third step, of forming a diffusion layer in an upper portion of the fin-shaped semiconductor layer, in a lower portion of the first pillar-shaped semiconductor layer, and in a lower portion of the second pillar-shaped semiconductor layer,
a fifth step, following the fourth step, of depositing a first interlayer insulating film and exposing upper portions of the first dummy gate, the second dummy gate, the third dummy gate, and the fourth dummy

Assignees

• Unisantis Elect Singapore Pte

Inventors

• Masuoka Fujio
• Nakamura Hiroki

Classifications

• H10P14/3436

  being chalcogenide semiconductor materials not being oxides, e.g. ternary compounds · CPC title

• H10P14/2919

  being chalcogenide semiconducting materials not being oxides, e.g. ternary compounds · CPC title

• H10W10/0123

  using auxiliary pillars in the regions · CPC title

• H10W10/13

  formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI] · CPC title

• H01L45/1233 Primary

  Electricity · mapped topic