Reducing spin pumping induced damping of a free layer of a memory device

Patent metadata

Field	Value
Publication number	US-9929211-B2
Application number	US-23695608-A
Country	US
Kind code	B2
Filing date	Sep 24, 2008
Priority date	Sep 24, 2008
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

A system and method of reducing spin pumping induced damping of a free layer of a memory device is disclosed. The memory device includes an anti-ferromagnetic material (AFM) pinning layer in contact with a bit line access electrode. The memory device also includes a pinned layer in contact with the AFM pinning layer, a tunnel barrier layer in contact with the pinned layer, and a free layer in contact with the tunnel barrier layer. The memory device includes a spin torque enhancing layer in contact with the free layer and in contact with an access transistor electrode. The spin torque enhancing layer is configured to substantially reduce spin pumping induced damping of the free layer.

First claim

What is claimed is:

1. A memory device comprising:
a bit line access electrode in contact with a bit line;
an anti-ferromagnetic material (AFM) pinning layer in contact with the bit line access electrode;
a pinned layer in contact with the AFM pinning layer;
a tunnel barrier layer in contact with the pinned layer;
a free layer in contact with the tunnel barrier layer;
a spin torque enhancing layer in contact with the free layer, wherein the spin torque enhancing layer comprises magnesium oxide (MgO) and wherein the spin torque enhancing layer further comprises at least one of silver oxide (AgO), arsenic oxide (AsO), cadmium oxide (CdO), gallium oxide (GaO), mercury oxide (HgO), indium oxide (InO), iridium oxide (IrO), osmium oxide (OsO), palladium oxide (PdO), antimony oxide (SbO), and tellurium oxide (TeO); and
an access transistor electrode in contact with the spin torque enhancing layer and in contact with a substrate.

2. The memory device of claim 1 , wherein the spin torque enhancing layer has a thickness greater than 5 nanometers (nm) and less than or equal to 10 nm, and wherein the free layer is deposited on the spin torque enhancing layer earlier in a fabrication process than depositing of the pinned layer.

3. The memory device of claim 1 , wherein a data value is read in response to a read current applied between the bit line access electrode and the access transistor electrode.

4. The memory device of claim 3 , wherein the read current flows through the bit line access electrode and the AFM pinning layer to detect a resistance corresponding to an orientation of magnetic moments of the free layer and the pinned layer.

5. The memory device of claim 1 , wherein the memory device is an element of a spin torque tunneling magnetic tunneling junction (STT-MTJ) device.

6. The memory device of claim 1 , wherein the pinned layer comprises a first pinned layer and a second pinned layer between the first pinned layer and a third pinned layer, and wherein the first pinned layer consists essentially of Cobalt (Co), Iron (Fe), and Boron (B).

7. The memory device of claim 6 , wherein the second pinned layer consists essentially of Ruthenium (Ru), and wherein the second pinned layer is in contact with the first pinned layer.

8. The memory device of claim 7 , wherein the third pinned layer consists essentially of Cobalt (Co) and Iron (FE) and is in contact with the second pinned layer.

9. The memory device of claim 1 , wherein the tunnel barrier layer comprises Magnesium Oxide (MgO).

10. A method of forming a memory device, the method comprising:
depositing a spin torque enhancing layer on an access transistor electrode that is in contact with a substrate, wherein the spin torque enhancing layer comprises magnesium oxide (MgO) and wherein the spin torque enhancing layer further comprises at least one of silver oxide (AgO), arsenic oxide (AsO), cadmium oxide (CdO), gallium oxide (GaO), mercury oxide (HgO), indium oxide (InO), iridium oxide (IrO), osmium oxide (OsO), palladium oxide (PdO), antimony oxide (SbO), and tellurium oxide (TeO);
after depositing the spin torque enhancing layer, depositing a free layer on the spin torque enhancing layer;
after depositing the free layer, depositing a spacer layer on the free layer;
after depositing the spacer layer, depositing a pinned layer on the spacer layer;
after depositing the pinned layer, depositing an anti-ferromagnetic material (AFM) pinning layer on the pinned layer; and
after depositing the AFM pinning layer, depositing a bit line access electrode that is in contact with a bit line.

11. The method of claim 10 , wherein the spin torque enhancing layer further comprises a half-metallic material and has a thickness greater than 7 nanometers (nm) and less than or equal to 10 nm.

12. The method of claim 10 , wherein the free layer comprises a synthetic ferromagnetic material, and wherein the free layer is deposited on the spin torque enhancing layer earlier in a fabrication process than depositing the pinned layer.

13. The method of claim 10 , wherein the spacer layer comprises a tunnel barrier layer.

14. A magnetic tunneling junction (MTJ) structure comprising:
a bit line access electrode in contact with a bit line;
an anti-ferromagnetic material (AFM) pinning layer in contact with the bit line access electrode;
a pinned layer in contact with the AFM pinning layer;
at least one layer comprising a tunnel barrier layer in contact with the pinned layer;
a free layer in contact with the at least one layer comprising the tunnel barrier layer;
a spin torque enhancing layer in contact with the free layer, wherein the spin torque enhancing layer comprises magnesium oxide (MgO) and wherein the spin torque enhancing layer further comprises at least one of silver oxide (AgO), arsenic oxide (AsO), cadmium oxide (CdO), gallium oxide (GaO), mercury oxide (HgO), indium oxide (InO), iridium oxide (IrO), osmium oxide (OsO), palladium oxide (PdO), antimony oxide (SbO), and tellurium oxide (TeO); and
an access transistor electrode that is in contact with the spin torque enhancing layer and in contact with a substrate.

15. The memory device of claim 1 , wherein the spin torque enhancing layer further comprises an oxide of copper (Cu).

16. The MTJ structure of claim 14 , wherein the spin torque enhancing layer has a thickness greater than 7 nanometers (nm) and less than or equal to 10 nm, and wherein the free layer is deposited on the spin torque enhancing layer earlier in a fabrication process than depositing of the pinned layer.

17. An apparatus comprising:
means for passing a read current through a bit line access electrode of a memory device and through an anti-ferromagnetic material (AFM) pinning layer, wherein the bit line access electrode is in contact with a bit line; and
means for detecting a resistance corresponding to a relative orientation of a first magnetic moment of a free layer that is in contact with a spin torque enhancing layer to a second magnetic moment of a pinned layer, the spin torque enhancing layer comprising magnesium oxide (MgO), the pinned layer in contact with the AFM pinning layer and in contact with a tunnel barrier layer, wherein the tunnel barrier layer is in contact with the free layer, wherein the free layer is in contact with the spin torque enhancing layer, and wherein the spin torque enhancing layer is in contact with an access transistor electrode that is in contact with a substrate.

18. A non-transitory computer-readable medium storing instructions comprising:
instructions that, when executed by a processor, cause the processor to:
pass a read current through a bit line access electrode of a memory device and through an anti-ferromagnetic material (AFM) pinning layer, wherein the bit line access electrode is in contact with a bit line; and
detect a resistance corresponding to a relative orientation of a first magnetic moment of a free layer that is in contact with a spin torque enhancing layer to a second magnetic moment of a pinned layer, the pinned layer in contact with the AFM pinning layer, wherein the pinned layer is in contact with a tunnel barrier layer, wherein the tunnel barrier layer is in contact with the free layer, wherein the free layer is in contact with the spin torque enhancing layer, wherein the spin torque enhancing layer comprises magnesium oxide (MgO), and wherein the spin torque enhancing layer is in contact with an access transistor electrode in contact with a substrate.

19. A memory device comprising:
a bit line access electrode in

Assignees

• Zhu Xiaochun
• Kang Seung H
• Li Xia
• Qualcomm Inc

Inventors

• Zhu Xiaochun
• Kang Seung H
• Li Xia

Classifications

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L27/228 Primary

  Electricity · mapped topic

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• H01L43/08

  Electricity · mapped topic