Isolation structure for IC with EPI regions sharing the same tank

Patent metadata

Field	Value
Publication number	US-9929140-B2
Application number	US-201514713785-A
Country	US
Kind code	B2
Filing date	May 15, 2015
Priority date	May 22, 2014
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.

First claim

The invention claimed is:

1. A method of isolating devices within a common tank, comprising:
forming a blanket n+ buried layer (NBL) in a p-epi layer on a substrate, said NBL defining a buried portion of said p-epi layer (buried p-epi layer) below said NBL;
forming an outer deep trench (DT) isolation ring (outer DT ring) in said p-epi layer by forming a trench, lining said trench with a dielectric liner to form dielectric sidewalls, and filling said trench;
forming a first DEEPN diffusion region by n-type implanting along said dielectric sidewalls of said outer DT ring and annealing to form said first DEEPN diffusion region contacting said dielectric sidewalls of said outer DT ring and extending downward from a topside surface of said p-epi layer to said NBL, said first DEEPN diffusion region configured as a ring (DEEPN ring) circumscribed by said dielectric sidewalls of said outer DT ring, and said DEEPN ring enclosing a portion of said p-epi layer to define an enclosed p-epi region within;
simultaneously, while forming said outer DT ring, forming a plurality of inner DT structures within said enclosed p-epi region, each inner DT structure comprising dielectric sidewalls; and
simultaneously, while forming said first DEEPN diffusion region, forming, for each of said inner DT structures, a second DEEPN diffusion region contacting said dielectric sidewalls of said inner DT structure and extending downward from said topside surface of said p-epi layer to said NBL, said plurality of inner DT structures arranged with a spacing so that adjacent ones of said second DEEPN diffusion regions overlap to form a continuous wall of n-type material which extends from a first side to a second side of said outer DT ring to divide said enclosed p-epi region into a first p-epi region and a second p-epi region;
wherein said NBL in said first p-epi region connects to said NBL in said second p-epi region.

2. The method of claim 1 , wherein a depth of said outer DT ring and said plurality of inner DT structures is greater than a depth of said NBL.

3. The method of claim 1 , wherein each inner DT structure collectively by itself forms a closed shape inside said outer DT ring.

4. The method of claim 1 , further comprising forming a first NPN electrostatic discharge (ESD) device in said first p-epi region and a second NPN ESD device in said second p-epi region, said first NPN ESD device and said second NPN ESD device being connected to one another through said NBL to provide either a bidirectional ESD cell or a back-to-back ESD cell.

5. The method of claim 1 , wherein a center-to-center spacing between adjacent ones of said inner DT structures is between 1.5 μm and 3 μm.

6. The method of claim 1 , wherein a width of each inner DT structure is between 2 μm and 3 μm.

7. The method of claim 1 , wherein said substrate comprises p-doped silicon having a doping level from 1×10 16 to 1×10 19 cm −3 , said p-epi layer comprises silicon that is 6 μm to 12 μm thick, and said buried p-epi layer has a doping level from 3×10 14 cm −3 to 3×10 16 cm −3 .

8. The method of claim 2 , wherein filling said trench of said outer DT ring comprises filling said trench with p-doped polysilicon to provide contact to said buried p-epi layer, and wherein forming said plurality of inner DT structures comprises filling an inside of each of said plurality of inner DT structures with p-doped polysilicon.

9. The method of claim 1 , wherein said plurality of inner DT structures is spaced from one another by said second DEEPN diffusion regions.

10. The method of claim 1 , wherein said dielectric sidewalls of at least one of the inner DT structures does not directly contact said DEEPN ring.

11. The method of claim 1 , wherein said second DEEPN diffusion regions have a depth that is less than a depth of said inner DT structures.

12. A method of isolating devices within a common tank, comprising:
forming a blanket n+ buried layer (NBL) in a p-epi layer on a substrate, wherein the NBL defines a buried portion of the p-epi layer (buried p-epi layer) below the NBL, and wherein the p-epi layer comprises an upper p-doped layer;
forming an outer deep trench (DT) isolation ring (outer DT ring) in the p-epi layer by forming a trench and then forming dielectric sidewalls in the trench;
forming a first DEEPN diffusion region by n-type implanting along the dielectric sidewalls of the outer DT ring and annealing to form the first DEEPN diffusion region that contacts the dielectric sidewalls of the outer DT ring and extends downward from the upper p-doped layer of the p-epi layer to the NBL, wherein the first DEEPN diffusion region is configured as a ring (DEEPN ring) circumscribed by the dielectric sidewalls of the outer DT ring, the DEEPN ring enclosing a portion of the p-epi layer to define an enclosed p-epi region within;
while forming the outer DT ring, forming a plurality of inner DT structures within the enclosed p-epi region, each inner DT structure comprising dielectric sidewalls; and
while forming the first DEEPN diffusion region, forming, for each of the inner DT structures, a second DEEPN diffusion region that contacts the dielectric sidewalls of the inner DT structure and extends downward from the upper p-doped layer of the p-epi layer to the NBL;
wherein each inner DT structure extends deeper into the p-epi layer than its respective second DEEPN diffusion region, and the inner DT structures are spaced so that adjacent ones of the second DEEPN diffusion regions overlap to form a continuous wall of n-type material extending from a first side of the outer DT ring to a second side of the outer DT ring to divide the enclosed p-epi region into a first p-epi region and a second p-epi region.

13. The method of claim 12 , wherein the NBL in the first p-epi region is connected to the NBL in the second p-epi region.

14. The method of claim 12 , comprising forming a surface nwell region in the upper p-doped layer of the p-epi layer, the first DEEPN diffusion region contacting the surface n-well region and extending downward from the surface nwell region to the NBL.

15. The method of claim 14 , comprising forming an n+ contact in the upper p-doped layer and over the surface nwell region, the n+ contact being connected to the first DEEPN diffusion region by the surface nwell region.

16. The method of claim 12 , wherein forming the dielectric sidewalls in the trench of the outer DT ring comprises forming a dielectric liner in the trench, and wherein forming the outer DT ring further comprises filling the trench with p-doped polysilicon after forming the dielectric liner.

17. The method of claim 16 , comprising forming a p+ contact in the upper p-doped layer over the outer DT ring, the p+ contact being connected to the buried p-epi layer by the p-doped polysilicon.

18. The method of claim 12 , comprising forming a first NPN electrostatic discharge (ESD) device in the first p-epi region and a second NPN ESD device in the second p-epi region, the first NPN ESD device and the second NPN ESD device being connected to one another through the NBL to provide either a bidirectional ESD cell or a back-to-back ESD cell.

19. The method of claim 12 , wherein the outer DT ring has a ring shape comprising four sides, the four sides including the first side and the second side, and the first side and the second side being opposite from each other.

20. The method of claim 12 , wherein the outer DT ring has a ring shape comprising four sides, the four sides including the first side and the second side, and th

Assignees

• Texas Instruments Inc

Inventors

• Edwards Henry Litzmann
• Salman Akram A
• Hu Binghua

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10W10/0148

  comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers · CPC title

• H10W10/041

  of isolation regions comprising polycrystalline semiconductor materials · CPC title