Method for manufacturing ESD protection device

Patent metadata

Field	Value
Publication number	US-9929137-B2
Application number	US-201715606976-A
Country	US
Kind code	B2
Filing date	May 26, 2017
Priority date	May 27, 2016
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

Disclosed is a method for manufacturing an ESD protection device. The method comprises: forming a first buried layer on the semiconductor substrate; forming a first epitaxial layer on the semiconductor substrate; forming a first doped region in the first epitaxial layer and forming a second doped region surrounding the first doped region in the first epitaxial layer, wherein the semiconductor substrate and the first doped region are both of a first doping type, the buried layer and the first epitaxial layer are both of a second doping type, the first doping type is opposite to the second doping type, the first doped region and the second doped region are formed using a same first mask. The method uses the same mask to form an emitter region of the open-base bipolar transistor, and to form a barrier doped region at the periphery of the emitter region, so that the manufacture cost is reduced and the parasitic capacitance of the ESD protection device is decreased.

First claim

The invention claimed is:

1. A method for manufacturing an ESD protection device, comprising:
forming a first buried layer on a semiconductor substrate;
forming a first epitaxial layer on said semiconductor substrate;
forming a first doped region in said first epitaxial layer; and
forming a second doped region in said first epitaxial layer which surrounds said first doped region,
wherein said semiconductor substrate and said first doped region are both of a first doping type, said buried layer and said first epitaxial layer are both of a second doping type, said first doping type and said second doping type are opposite,
said first doped region and said second doped region are formed using a same first mask.

2. The method according to claim 1 , further comprising:
forming said first mask on said first epitaxial layer before forming said first doped region, wherein said first mask has a first opening corresponding to said first doped region.

3. The method according to claim 2 , further comprising:
enlarging size of said first opening to expose a portion of said surface of said first epitaxial layer surrounding said first doped region between said steps of forming said first doped region and forming said second doped region.

4. The method according to claim 3 , wherein said size of said first opening is enlarged by reactive ion etching.

5. The method according to claim 1 , wherein said semiconductor substrate and said first doped region are used as a collector region and an emitter region of an open-base bipolar transistor, respectively, said first buried layer and said first epitaxial layer are used together as a base region of said open-base bipolar transistor.

6. The method according to claim 1 , further comprising:
forming a second buried layer in said semiconductor substrate;
forming a second epitaxial layer on said semiconductor substrate; and forming a third doped region in said second epitaxial layer,
wherein said second buried layer and said second epitaxial layer are of said first doping type, and said third doped region is of said second doped type.

7. The method according to claim 6 , wherein said first epitaxial layer and said second epitaxial layer are both formed by a same step of epitaxial growth.

8. The method according to claim 7 , wherein said first epitaxial layer and said second epitaxial layer are self-doped by said first buried layer and said second buried layer, respectively.

9. The method according to claim 6 , wherein said first epitaxial layer and said first doped region are used as a cathode and an anode of a rectification device, respectively.

10. The method according to claim 6 , further comprising: after said steps of forming a first doped region, forming a second doped region and forming a third doped region,
forming an interlayer dielectric layer on surfaces of said first epitaxial layer, said first doped region, said second doped region and said third doped region;
forming conductive vias in said interlayer dielectric layer which respectively reaches said first doped region and said third doped region; forming a first electrode on said interlayer dielectric layer which is electrically coupled to said conductive vias; and
forming a second electrode on a surface of said semiconductor substrate opposite to said first electrode.

11. The method according to claim 6 , further comprising: after said steps of forming a first doped region, forming a second doped region and forming a third doped region,
forming an isolation structure extending from said surfaces of said first epitaxial layer and said second epitaxial layer into said semiconductor substrate for defining said respective active regions of said rectification device and said open-base bipolar transistor.

Assignees

• Silergy Semiconductor Technology Hangzhou Ltd

Inventors

• Yin Dengping
• Wang Shijun
• Yao Fei

Classifications

• H10D8/00

  Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title

• H10W42/80

  protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W42/60 Primary

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H01L23/62

  Electricity · mapped topic

• H01L23/60

  Electricity · mapped topic