Symmetric bit coding for printed memory devices
US-2017068830-A1 · Mar 9, 2017 · US
US9928893B1 · US · B1
| Field | Value |
|---|---|
| Publication number | US-9928893-B1 |
| Application number | US-201715613668-A |
| Country | US |
| Kind code | B1 |
| Filing date | Jun 5, 2017 |
| Priority date | Jun 5, 2017 |
| Publication date | Mar 27, 2018 |
| Grant date | Mar 27, 2018 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A circular memory device includes a plurality of bottom electrodes, a plurality of top electrodes, a ferroelectric layer, and a plurality of memory storage locations within the ferroelectric layer at a crossover point of each of the bottom electrodes and each top electrode. Contact pads of the bottom electrodes and top electrodes may include a perimeter that defines an annular sector that allows a memory operation to be performed on the circular memory device across a range of rotational positions. In an example implementation, the memory operation may be performed on the circular memory device regardless of the rotational orientation of the circular memory device relative to a reader.
Opening claim text (preview).
The invention claimed is: 1. A memory device, comprising: a plurality of bottom electrodes comprising a plurality of bottom electrode contact pads and a plurality of bottom electrode extended members, wherein: each of the plurality of bottom electrode contact pads is in electrical communication with one of the bottom electrode extended members; each of the plurality of bottom electrode contact pads comprises a first arc-shaped midline bisecting the bottom electrode contact pad and positioned at a first radius from a center of the memory device; and a perimeter of each bottom electrode contact pad defines an annular sector bisected by the first arc-shaped midline; a plurality of top electrodes comprising a plurality of top electrode contact pads and a plurality of top electrode extended members, wherein: each of the plurality of top electrode contact pads is in electrical communication with one of the top electrode extended members; each of the plurality of top electrode contact pads comprises a second arc-shaped midline bisecting the top electrode and positioned at a second radius from the center of the memory device, wherein the first radius is different from the second radius; and a ferroelectric layer positioned between the plurality of bottom electrode extended members and the plurality of top electrode extended members. 2. The memory device of claim 1 , wherein at least one of the plurality of bottom electrode extended members and the plurality of top electrode extended members are arranged in interleaving, non-intersecting spirals. 3. The memory device of claim 1 , wherein each of the plurality of top electrode extended members cross over every bottom electrode extended member of the plurality of bottom electrode extended members at a crossover point. 4. The memory device of claim 3 , further comprising a memory storage location positioned at every crossover point. 5. The memory device of claim 1 , wherein: at least one of the plurality of bottom electrode extended members and the plurality of top electrode extended members are arranged in interleaving, non-intersecting spirals; each of the plurality of top electrode extended members cross over every bottom electrode extended member of the plurality of bottom electrode extended members at a crossover point; and the memory device further comprises a memory storage location positioned at every crossover point. 6. The memory device of claim 1 , wherein the memory device comprises exactly five bottom electrodes and exactly five top electrodes, and each bottom electrode contact pad and each top electrode contact pad extends along an arc of from 52° to 62°. 7. The memory device of claim 1 , further comprising a center contact pad having a perimeter that defines a circle, wherein the center contact pad is electrically coupled with only one bottom electrode of the plurality of bottom electrodes. 8. The memory device of claim 7 , wherein the center contact pad and the only one bottom electrode electrically coupled therewith provides an orienting electrode configured to provide a rotational orientation of the memory device during a memory operation. 9. A memory system, comprising: a circular memory device, comprising: a plurality of bottom electrodes comprising a plurality of bottom electrode contact pads and a plurality of bottom electrode extended members, wherein: each of the plurality of bottom electrode contact pads is in electrical communication with one of the bottom electrode extended members; each of the plurality of bottom electrode contact pads comprises a first arc-shaped midline bisecting the bottom electrode contact pad and positioned at a first radius from a center of the circular memory device; and a perimeter of each bottom electrode contact pad defines an annular sector bisected by the first arc-shaped midline; a plurality of top electrodes comprising a plurality of top electrode contact pads and a plurality of top electrode extended members, wherein: each of the plurality of top electrode contact pads is in electrical communication with one of the top electrode extended members; each of the plurality of top electrode contact pads comprises a second arc-shaped midline bisecting the top electrode and positioned at a second radius from the center of the circular memory device, wherein the first radius is different from the second radius; and a ferroelectric layer positioned between the plurality of bottom electrode extended members and the plurality of top electrode extended members; and a reader configured to perform a memory operation on the circular memory device, the reader comprising a plurality of probes configured to electrically couple to the plurality of bottom electrode contact pads and the plurality of top electrode contact pads. 10. The memory system of claim 9 , the plurality of probes comprising a plurality of primary probes and a plurality of secondary probes, wherein: the plurality of secondary probes is configured to be inactive when each primary probe from the plurality of primary probes is in electrical communication with one of the bottom electrode contact pads or with one of the top electrode contact pads during the memory operation; and the plurality of primary probes is configured to be inactive, and the plurality of secondary probes is configured to perform the memory operation, when at least one of primary probes is not in electrical communication with one of the bottom electrode contact pads or with one of the top electrode contact pads during the memory operation. 11. The memory system of claim 10 , wherein: each bottom electrode contact pad and each top electrode contact pad extends along an arc of from 52° to 62°; and the plurality of secondary probes is rotationally offset from the plurality of primary probes by from 13° to 36°. 12. The memory system of claim 11 , wherein: the circular memory device further comprises a center contact pad comprising a perimeter that defines a circle; the center contact pad is electrically coupled with only one bottom electrode of the plurality of bottom electrodes; and the reader further comprises a center contact probe configured to electrically couple to the center contact pad during the memory operation. 13. The memory system of claim 9 , wherein at least one of the plurality of bottom electrode extended members and the plurality of top electrode extended members are arranged in interleaving, non-intersecting spirals. 14. The memory system of claim 9 , wherein each of the plurality of top electrode extended members cross over every bottom electrode extended member of the plurality of bottom electrode extended members at a crossover point. 15. The memory system of claim 14 , further comprising a memory storage location positioned at every crossover point. 16. The memory system of claim 9 , wherein: at least one of the plurality of bottom electrode extended members and the plurality of top electrode extended members are arranged in interleaving, non-intersecting spirals; each of the plurality of top electrode extended members cross over every bottom electrode extended member of the plurality of bottom electrode extended members at a crossover point; and the circular memory device further comprises a memory storage location positioned at every crossover point. 17. A method for performing a memory operation on a circular memory device, comprising: placing a reader in physical contact with the circular memory device; detecting whether every primary probe of a plurality of primary probes of the reader is electr
Electricity · mapped topic
using ferroelectric capacitors · CPC title
Reading or sensing circuits or methods · CPC title
Integrated device layouts · CPC title
using ferroelectric record carriers; Record carriers therefor · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.