Memory apparatuses having ground switches

Patent metadata

Field	Value
Publication number	US-9928892-B2
Application number	US-201615153866-A
Country	US
Kind code	B2
Filing date	May 13, 2016
Priority date	Aug 20, 2015
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

A resistive memory apparatus includes a memory cell array having a plurality of memory cells and a first ground switch. The plurality of memory cells are arranged in a plurality of rows and a plurality of columns, and each memory cell in a first column of the plurality of memory cells is connected between a first bitline and a first source line. The first ground switch is connected in parallel with the first source line, and the first ground switch is configured to selectively provide a first current path from the first bitline to ground through a selected memory cell in the first column of the plurality of memory cells and the first source line, the current path traversing only a portion of the first source line.

First claim

What is claimed is:

1. A memory apparatus comprising:
a plurality of memory cells arrayed in a plurality of rows and a plurality of columns, each of the plurality of memory cells including a cell transistor and a memory element;
a plurality of bitlines, each of the plurality of bitlines connected to memory elements of memory cells in a corresponding column of memory cells;
a plurality of source lines, each of the plurality of source lines connected to sources of cell transistors of memory cells in a corresponding column of memory cells;
at least one first ground switch including a first transistor connected between a first ground line and a source of a cell transistor of a first memory cell from among memory cells in a first of the plurality of columns, a gate of the first transistor connected to a first of the plurality of bitlines; and
at least one second ground switch including a second transistor connected between a second ground line and the first of the plurality of bitlines, a gate of the second transistor connected to a first of the plurality of source lines; wherein
the at least one first ground switch further includes a third transistor adjacent to the first transistor, the third transistor and the first transistor commonly connected to the first ground line,
the third transistor is connected between the first ground line and a source of a cell transistor of a second memory cell from among the memory cells in the first of the plurality of columns, and
a gate of the third transistor is connected to the first of the plurality of bitlines.

2. The memory apparatus of claim 1 , wherein the first ground line and the second ground line are a common ground line.

3. The memory apparatus of claim 1 , wherein the memory element comprises:
a magnetic tunnel junction (MTJ) having a magnetoresistive element.

4. A memory apparatus comprising:
a plurality of memory cells arrayed in a plurality of rows and a plurality of columns, each of the plurality of memory cells including a cell transistor and a memory element;
a plurality of bitlines, each of the plurality of bitlines connected to memory elements of memory cells in a corresponding column of memory cells;
a plurality of source lines, each of the plurality of source lines connected to sources of cell transistors of memory cells in a corresponding column of memory cells;
at least one first ground switch including a first transistor connected between a first ground line and a source of a cell transistor of a first memory cell from among memory cells in a first of the plurality of columns, a gate of the first transistor connected to a first of the plurality of bitlines; and
at least one second ground switch including a second transistor connected between a second ground line and the first of the plurality of bitlines, a gate of the second transistor connected to a first of the plurality of source lines; wherein
the at least one second ground switch further includes a third transistor adjacent to the second transistor, the third transistor and the second transistor commonly connected to the second ground line,
the third transistor is connected between the second ground line and the first of the plurality of bitlines, and
a gate of the third transistor is connected to the first of the plurality of source lines.

5. The memory apparatus of claim 4 , wherein sources of the second and third transistors connected to the second ground line are impurity regions separated by an isolation region.

6. The memory apparatus of claim 4 , wherein sources of the second and third transistors connected to the second ground line are formed as one impurity region.

7. The memory apparatus of claim 4 , wherein
a width of the gate of each of the second and third transistors is substantially the same as a width of a gate of the cell transistor of the first memory cell; and
a length of the gates of each of the second and third transistors is substantially the same as a length of the gate of the cell transistor of the first memory cell.

8. A memory apparatus comprising:
a plurality of memory cells arrayed in a plurality of rows and a plurality of columns, each of the plurality of memory cells including a cell transistor and a memory element;
a plurality of bitlines, each of the plurality of bitlines connected to memory elements of memory cells in a corresponding column of memory cells;
a plurality of source lines, each of the plurality of source lines connected to sources of cell transistors of memory cells in a corresponding column of memory cells;
at least one first ground switch including a first transistor connected between a first ground line and a source of a cell transistor of a first memory cell from among memory cells in a first of the plurality of columns, a gate of the first transistor connected to a first of the plurality of bitlines;
at least one second ground switch including a second transistor connected between a second ground line and the first of the plurality of bitlines, a gate of the second transistor connected to a first of the plurality of source lines;
a plurality of complementary bitlines, each of the plurality of complementary bitlines paired with a corresponding one of the plurality of bitlines;
a second memory cell corresponding to the first memory cell, the second memory cell connected to a first of the plurality of complementary bitlines, the first of the plurality of complementary bitlines corresponding to the first of the plurality of bitlines; and
wherein the at least one first ground switch further includes
a third transistor connected between the first ground line and a source of a cell transistor of the second memory cell, wherein
a gate of the third transistor is connected to the first of the plurality of complementary bitlines.

9. The memory apparatus of claim 8 , wherein the at least one second ground switch further comprises:
a fourth transistor connected between the second ground line and the first of the plurality of complementary bitlines; wherein
a gate of the fourth transistor is connected to the first of the plurality of source lines.

Assignees

• Seo Bo Young
• Chung Yong Seok
• Koh Gwan Hyeob
• Lee Yong Kyu
• Samsung Electronics Co Ltd

Inventors

• Seo Bo-Young
• Chung Yong-Seok
• Koh Gwan-Hyeob
• Lee Yong-Kyu

Classifications

• G11C11/1675 Primary

  Writing or programming circuits or methods · CPC title

• H01L27/228

  Electricity · mapped topic

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C11/1659

  Cell access · CPC title

• H01L43/08

  Electricity · mapped topic