MISO equalization with ADC averaging

Patent metadata

Field	Value
Publication number	US-9928854-B1
Application number	US-201715586217-A
Country	US
Kind code	B1
Filing date	May 3, 2017
Priority date	May 3, 2017
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

An apparatus may include a circuit configured to generate a set of first ADC samples based on a first signal associated with a first read head position and a failed segment and to generate a set of second ADC samples based on a second signal associated with a second read head position and the failed segment. The circuit may then generate, by a MISO equalizer, a set of equalized ADC samples based on the set of first ADC samples and the set of second ADC samples.

First claim

What is claimed is:

1. An apparatus comprising:
a circuit configured to:
generate a set of first ADC samples based on a first signal associated with a first read head position and a failed segment;
generate a set of second ADC samples based on a second signal associated with a second read head position and the failed segment; and
generate, by a MISO equalizer, a set of equalized ADC samples based on the set of first ADC samples and the set of second ADC samples.

2. The apparatus of claim 1 , further comprising the circuit further configured to generate an output signal as a plurality of bit values based on the set of equalized ADC samples.

3. The apparatus of claim 1 , further comprising the circuit configured to:
perform the generation of the set of first ADC samples based on an analog signal from a first read head; and
perform the generation of the set of second ADC samples based on an analog signal from a second read head.

4. The apparatus of claim 3 , further comprising the circuit further configured to:
perform the generation of the set of first ADC samples when the first read head is positioned at a first offset from a center of a track corresponding to the failed segment and the second read head is positioned at a second offset from the center of the track, the first offset being different than the second offset.

5. The apparatus of claim 3 , further comprising the circuit further configured to:
generate another set of first ADC samples based on the first signal associated with the first read head position and the failed segment;
generate a set of averaged first ADC samples based on the set of first ADC samples and the other set of first ADC samples;
generate another set of second ADC samples based on the second signal associated with the second read head position and the failed segment;
generate a set of averaged second ADC samples based on the set of second ADC samples and the other set of second ADC samples; and
perform the generation, by the MISO equalizer, of the set of equalized ADC samples based on the set of first averaged ADC samples and the set of second ADC samples using the set of averaged first ADC samples and the set of averaged second ADC samples.

6. The apparatus of claim 5 , further comprising the circuit further configured to:
adapt the generation, by the MISO equalizer, of the one or more equalized ADC samples using the set of averaged first ADC samples and the set of averaged second ADC samples.

7. The apparatus of claim 1 , further comprising the
perform the generation of the set of first ADC samples based on an analog signal from a first read head;
perform the generation of the set of second ADC samples based on an analog signal from a second read head; and
perform the generation of the set of first ADC samples and the generation of the set of second ADC samples when the first read head is positioned at a first offset from a center of a track corresponding to the failed segment and the second read head is positioned at a second offset from the center of the track, the first offset being different than the second offset.

8. The apparatus of claim 1 , further comprising the circuit configured to:
perform the generation, by the MISO equalizer, of the set of equalized ADC samples by inputting, to the MISO equalizer, the set of first ADC samples, the set of second ADC samples and another set of equalized ADC samples for the failed segment previously generated by the MISO equalizer.

9. The apparatus of claim 1 , further comprising the circuit configured to:
attempt decoding of the one or more equalized ADC samples; and
halt generation of additional sets of first ADC samples and additional sets of second ADC samples when the attempted decoding is successful.

10. The apparatus of claim 5 , further comprising the circuit further configured to:
generate hard decision data based on at least one of the set of first ADC samples and the set of second ADC samples; and
adapt the MISO equalizer using the set of first ADC samples and set of second ADC samples, the hard decision data and another set of equalized ADC samples for the failed segment previously generated by the MISO equalizer.

11. A system comprising:
one or more ADC circuits configured to:
generate a plurality of sets of first ADC samples based on a first signal associated with a first read head position and a failed segment; and
generate a plurality of sets of second ADC samples based on a second signal associated with a second read head position and the failed segment;

one or more accumulator circuits configured to:
generate averaged first ADC samples based on the plurality of sets of first ADC samples; and
generate averaged second ADC samples based on the plurality of sets of second ADC samples; and

a MISO equalizer configured to:
generate one or more equalized ADC samples based on the averaged first ADC samples and the averaged second ADC samples.

12. The system of claim 11 further comprising:
a decoder circuit configured to generate an output signal as a plurality of bit values based on the equalized ADC samples.

13. The system of claim 11 further comprising:
a circuit configured to move a read head array subsequent to the generation of the plurality of sets of first ADC samples and prior to the generation of the plurality of sets of second ADC samples.

14. The system of claim 13 further comprising the one or more ADC circuits configured to:
perform the generation of the plurality of sets of first ADC samples based on an analog signal from a first read head when the first read head is positioned at a first offset from a center of a track corresponding to the failed segment and the second read head is positioned at a second offset from the center of the track, the first offset being different than the second offset; and
perform the generation of the plurality of sets of second ADC samples based on an analog signal from a second read head when the second read head is positioned at a third offset from the center of the track corresponding to the failed segment and the first read head is positioned at a fourth offset from the center of the track, the third offset being different than the fourth offset.

15. The system of claim 11 further comprising:
a first read head configured to generate the first signal; and
a second read head configured to generate the second signal.

16. A system comprising:
one or more ADC circuits configured to:
generate a set of first ADC samples based on a first signal associated with a first read head position and a failed segment; and
generate a set of second ADC samples based on a second signal associated with a second read head position and the failed segment; and

a MISO equalizer configured to:
generate a set of equalized ADC samples based on the set of first ADC samples and the set of second ADC samples.

17. The system of claim 16 further comprising:
the one or more ADC circuits further configured to:
generate another set of first ADC samples based on the first signal associated with the first read head position and the failed segment; and
generate another set of second ADC samples based on the second signal associated with the second read head position and the failed segment; and

the MISO equalizer further configured to:
generate another set of equalized ADC samples based on:
the other set of first ADC samples;
the other set of second ADC samples; and
the set of equalized ADC samples.

18. The system of claim 17 further comprising:
the one or more ADC circu

Assignees

• Seagate Technology Llc

Inventors

• Jury Jason Charles
• Marrow Marcus
• Link Michael J
• Bellorado Jason

Classifications

• G11B2005/0013

  of transducers, e.g. linearisation, equalisation · CPC title

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G11B5/012 Primary

  Recording on, or reproducing or erasing from, magnetic disks (G11B17/00, G11B19/00 take precedence) · CPC title

• G11B5/09 Primary

  Digital recording · CPC title

• G11B21/106

  on disks · CPC title