Decompression and traversal of a bounding volume hierarchy

Patent metadata

Field	Value
Publication number	US-9928640-B2
Application number	US-201514975294-A
Country	US
Kind code	B2
Filing date	Dec 18, 2015
Priority date	Dec 18, 2015
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

Embodiments provide for a graphics processing apparatus including a graphics processing unit having bounding volume logic to operate on a compressed bounding volume hierarchy, wherein each bounding volume node stores a parent bounding volume and multiple child bounding volumes that are encoded relative to the parent bounding volume.

First claim

What is claimed is:

1. A graphics processing apparatus comprising:
a set of registers to store configuration data and operational data for the graphics processing apparatus; and
bounding volume logic coupled to the set of registers, the bounding volume logic to encode multiple child bounding volumes relative to a reference bounding volume and separate of other child bounding volumes with the reference bounding volume being encoded using floating point values and the multiple child bounding volumes being encoded using fixed point values and to store the encoded multiple child bounding volumes in the set of registers for later ray traversal.

2. The graphics processing apparatus as in claim 1 , wherein the bounding volume logic is configured to encode the reference bounding volume and child bounding volumes using lower and upper bounds in multiple directions.

3. The graphics processing apparatus as in claim 2 , wherein the bounding volume logic is additionally configured to support a composite floating point data block for the reference bounding volume that includes a sign bit, a variable sized signed integer exponent, and a variable sized mantissa.

4. The graphics processing apparatus as in claim 1 , wherein the bounding logic is additionally configured to encode the reference bounding volume as lower bounds and scaled extents of the bounds and the child bounding volumes using lower and upper bounds in multiple directions.

5. The graphics processing apparatus as in claim 4 , wherein the bounding logic is additionally configured to encode the lower bounds of the reference bounding volume and scaled extents using floating point values and the relative child bounding volume using fixed point values.

6. The graphics processing apparatus as in claim 4 , wherein the reference bounding logic is additionally configured to encode lower bounds of the reference bounding volume using floating point values, the scaled extent as a power of 2, and the child bounding volume using fixed point values.

7. The graphics processing apparatus as in claim 1 , wherein each reference bounding plane stores an index of an equal child bounding plane without storing the equal child bounding plane.

8. The graphics processing apparatus as in claim 7 , wherein the bounding volume logic is additionally configured to use the encoded multiple child bounding volumes to encode nodes of a bounding volume hierarchy.

9. The graphics processing apparatus as in claim 8 additionally including ray tracing logic to perform ray traversal through the bounding volume hierarchy, the ray tracing logic to test if a ray intersects the encoded child bounding volumes of a node.

10. The graphics processing apparatus as in claim 9 , wherein the ray tracing logic is additionally configured to calculate bounding plane distances to test for ray bounding volume intersection via logic configured to:
calculate distances to the planes of the lower reference bounding planes; and
add to the distances a product of a reciprocal ray direction, scaled extents of the reference bounds, and the relative child hounding plane location, to calculate the distances to all child bounding planes.

11. A system on a chip integrated circuit including an application processor and a graphics processor, the integrated circuit comprising:
hounding volume logic to encode multiple child bounding volumes relative to a reference hounding volume and separate of other child bounding volumes with the reference bounding volume being encoded using floating point values and the multiple child bounding volume being encoded using fixed point values and to store the encoded multiple child bounding volumes in the set of registers for later ray traversal; and
ray tracing logic to perform ray traversal through a bounding volume hierarchy, the ray tracing logic to test if a ray intersects the encoded child bounding volumes of a node.

12. The system on a chip integrated circuit as in claim 11 , wherein the bounding logic is additionally configured to encode the reference bounding volume and child bounding volumes using lower and upper hounds in multiple directions.

13. The system on a chip integrated circuit as in claim 12 , wherein the bounding volume logic is additionally configured to encode the reference bounding volume using floating point values and the child bounding volume using fixed point values.

14. The system on a chip integrated circuit as in claim 11 , wherein the bounding logic is additionally configured to encode the reference bounding volume as lower hounds and scaled extents of the bounds and the child hounding volumes using lower and upper bounds in multiple directions.

15. The system on a chip integrated circuit as in claim 11 , wherein the ray tracing logic is additionally configured to calculate bounding plane distances to test for ray bounding volume intersection via logic configured to:
calculate distances to the planes of the lower reference bounding planes; and
add to the distances a product of a reciprocal ray direction, scaled extents of the reference bounds, and the relative child bounding plane location, to calculate the distances to all child bounding planes.

16. A graphics processing system comprising:
an application processor coupled to a graphics processor, wherein the application processor and the graphics processor are to perform processing operations including:
calculating a distance to a first bounding plane of a reference bounding volume of a bounding volume hierarchy, the reference bounding plane being defined by floating point values;
calculating the distance to a lower bounding plane of a child hounding volume using a decoded child bounding volume with fixed point values defined separate of other child bounding volumes relative to the reference bounding volume, the distance being based in part on the distance to the lower bounding plane of the reference bounding volume;
calculating the distance to an upper bounding plane of the child bounding volume using the decoded child bounding volume with fixed point values defined separate of other child bounding volumes relative to the reference bounding volume, the distance being based in part on the distance to the lower bounding plane of the reference bounding volume; and
determining a ray intersection for the decoded child bounding volume separate of other child bounding volumes and based in part on the distance to the upper and lower bounding plane of the child bounding volume.

17. The graphics processing system as in claim 16 , wherein the processing operations additionally include:
defining the reference bounding volume based in part on a bounding plane of the child bounding volume such that the reference bounding volume includes a shared bounding plane that is shared with the child bounding volume; and
encoding a value indicating that the shared bounding plane is associated with the child bounding volume.

18. The graphics processing system as in claim 17 , wherein the child bounding volume includes at least a first bounding plane and a second bounding plane, the first bounding plane is stored as a fixed point value and the second bounding plane is the shared bounding plane, wherein the shared bounding plane is not stored.

19. The graphics processing system as in claim 18 , wherein the processing operations additionally include performing a ray intersection test to determine the ray intersection for the child bounding volume.

20. The graphics processing system as in claim 19 , wherein during the ray intersection test, at leas

Assignees

• Intel Corp

Inventors

• Woop Sven
• Benthin Carsten
• Barringer Rasmus
• Akenine-Moller Tomas G

Classifications

• G06T15/08

  Volume rendering · CPC title

• G06T15/005

  General purpose rendering architectures · CPC title

• G06T15/06 Primary

  Ray-tracing · CPC title

• G06T2210/12

  Bounding box · CPC title

• G06T2210/08

  Bandwidth reduction · CPC title