Temperature-compliant integrated circuits

Patent metadata

Field	Value
Publication number	US-9928335-B2
Application number	US-201514728100-A
Country	US
Kind code	B2
Filing date	Jun 2, 2015
Priority date	Jun 2, 2015
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

Aspects of the present disclosure include a computer-implemented method for designing a temperature-compliant integrated circuit (IC). The method can include: calculating a thermal resistance of an IC layout, the IC layout having an area-dependent thermal conductance, a fin thermal conductance, and a gate thermal conductance each based on a device geometry of a plurality of transistors in the IC layout; calculating a self-heating temperature as directly proportional to the thermal resistance; comparing the self-heating temperature with a threshold temperature; in response to the self-heating temperature exceeding the threshold temperature, automatically modifying the device geometry of the IC layout to reduce at least one of the area term and the perimeter term, thereby reducing the self-heating temperature of the IC layout; and designing the temperature-compliant IC layout by repeating the calculating and automatically modifying steps until the self-heating temperature does not exceed the threshold temperature.

First claim

What is claimed is:

1. A computer-implemented method for designing a temperature-compliant integrated circuit (IC), the method comprising:
calculating a thermal resistance of an IC layout, the IC layout having an area-dependent thermal conductance, a gate thermal conductance, and a fin thermal conductance each based on a device geometry of a plurality of transistors in the IC layout, wherein the calculating includes:
calculating an area term for the IC layout, the area term being a product of a number of transistor gates, a number of fins per transistor gate, and the area-dependent thermal conductance of the IC layout,
calculating a perimeter term for the IC layout, the perimeter term being a product of the number of transistor gates and the gate thermal conductance of the IC layout, added to a product of the number of fins per transistor gate and the fin thermal conductance of the IC layout,
calculating a thermal conductance of the IC layout as a sum of the area term and the perimeter term, and
calculating the thermal resistance of the IC layout as an inverse of the thermal conductance;

calculating a self-heating temperature of the IC layout as directly proportional to the calculated thermal resistance;
comparing the self-heating temperature with a threshold temperature;
in response to the self-heating temperature exceeding the threshold temperature, automatically modifying the device geometry of the IC layout to reduce at least one of the area term and the perimeter term, thereby reducing the self-heating temperature of the IC layout;
designing the temperature-compliant IC layout by repeating the calculating and automatically modifying steps until the self-heating temperature does not exceed the threshold temperature; and
automatically fabricating, via an IC fabricator, an IC component having the temperature-compliant IC after the designing.

2. The method of claim 1 , wherein the thermal resistance (R th ) is calculated according to an equation:

R
th

=

1

G
th

=

1

(

Nfin
·
NF
·

G
thArea

)

+

(

(

Nfin
·

G
thNfin

)

+

(

NF
·

G
thNF

)

)

,

wherein G th represents the thermal conductance of the IC layout, Nfin represents the number of fins per transistor gate in the IC layout, NF represents the number of transistor gates in the IC layout, G thArea represents area-dependent thermal conductance of the IC layout, G thNfin represents the fin thermal conductance of the IC layout, and G thNF represents the gate thermal conductance of the IC layout.

3. The method of claim 1 , wherein the calculating of the self-heating temperature further includes multiplying the thermal resistance by a product of the number of transistor gates, the number of fins per transistor gate, and a power dissipated in each fin.

4. The method of claim 1 , wherein the calculating of the self-heating temperature (ΔT) based on the thermal resistance is calculated according to an equation:
Δ T=R th ( P diss,Fin ·NF·N fin),

wherein R th represents the thermal resistance of the IC layout, P diss,Fin represents a thermal power dissipated in each fin, NF represents the number of transistor gates in the IC layout, and Nfin represents the number of fins per transistor gate in the IC layout.

5. The method of claim 1 , wherein area-dependent thermal conductance, the fin thermal conductance, and the gate thermal conductance are at least partially derived from a local layout effect including a spacing between each adjacent FET in the IC layout and a voltage bias of each of each adjacent FET.

6. The method of claim 1 , wherein the area-dependent thermal conductance, the fin thermal conductance, and the gate thermal conductance are each at least partially derived from one of a fin height and a fin width of each of the plurality of FETs in the IC layout.

7. The method of claim 1 , wherein the area-dependent thermal conductance, the fin thermal conductance, and the gate thermal conductance are each at least partially derived from a back end of line (BEOL) wiring feature for the IC layout, the BEOL wiring feature being one of a total number of electrically connected vias and a metal contact layer width.

8. A system for designing a temperature-compliant integrated circuit (IC), the system comprising:
logic configured to calculate a thermal resistance of an IC layout, the IC layout having an area-dependent thermal conductance, a gate thermal conductance, and a fin thermal conductance each based on a device geometry of a plurality of transistors in the IC layout, wherein the calculating includes:
calculating an area term for the IC layout, the area term being a product of a number of transistor gates, a number of fins per transistor gate, and the transistor area-dependent thermal conductance of the IC layout, calculating a perimeter term for the IC layout, the perimeter term being a product of the number of transistor gates and the gate thermal conductance of the IC layout, added to a product of the number of fins per transistor gate and the fin thermal conductance of the IC layout,
calculating a thermal conductance of the IC layout as a sum of the area term and the perimeter term,
calculating the thermal resistance of the IC layout as an inverse of the thermal conductance,
calculating a self-heating temperature of the IC layout as directly proportional to the calculated thermal resistance, and
comparing the self-heating temperature with a threshold temperature;

an IC layout editor for, in response to the self-heating temperature exceeding the threshold temperature, automatically modifying the device geometry of the IC layout to reduce at least one of the area term and the perimeter term, thereby reducing the self-heating temperature of the IC layout; and designing the temperature-compliant IC layout by causing the logic to repeat the calculating steps, and repeating the automatic modifying of the IC layout, until the self-heating temperature do

Assignees

• Global Foundries Inc
• Globalfoundries Inc

Inventors

• Johnson James M
• Lee Sungjae
• Luo Lan
• Springer Scott K

Classifications

• G06F2119/08

  Thermal analysis or thermal optimisation · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F17/5081 Primary

  Physics · mapped topic