Microcomputer

Patent metadata

Field	Value
Publication number	US-9928184-B2
Application number	US-201314076252-A
Country	US
Kind code	B2
Filing date	Nov 10, 2013
Priority date	Nov 26, 2012
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

A microcomputer is provided for each of industrial apparatuses to synchronously control them and includes a CPU, a peripheral module, and a communication interface. The peripheral module controls an external apparatus based on a specified control parameter. The communication interface includes a time register that is synchronized with the other apparatuses in time series. The communication interface issues a CPU interrupt and a peripheral module interrupt to the CPU and the peripheral module, respectively, if a successively settled correction time matches the time register. In response to the peripheral module interrupt, the peripheral module changes the control parameter from a current value to an update value. In response to the CPU interrupt, the CPU starts an update program to calculate the next update value for the control parameter and writes the calculated value to the peripheral module.

First claim

What is claimed is:

1. A microcomputer comprising:
a CPU;
a peripheral module configured to generate an operation control signal to control operation of an external apparatus based on a value of an operation control parameter; and
a communication interface capable of communication with other devices via a network, wherein the communication interface includes a first register, a second register, and a comparison circuit, wherein the first and second registers hold times to synchronize with the other devices based on communication via the network,
wherein the comparison circuit compares a value held in the first register with a value held in the second register and, if a match is found, issues a CPU interrupt to the CPU, and issues a peripheral module interrupt to the peripheral module,
wherein the peripheral module includes a third register and a fourth register,
wherein the third register holds a current value of the operation control parameter,
wherein the fourth register holds an update value of the operation control parameter,
wherein the peripheral module generates the operation control signal to control operation of the external apparatus based on the current value of the operation control parameter,
wherein the CPU executes a parameter update program in response to the CPU interrupt to calculate the update value of the operation control parameter and write the update value to the fourth register,
wherein the peripheral module transfers the update value stored in the fourth register to the third register in response to the peripheral module interrupt to set the operation control signal according to the update value,
wherein the operation control signal is a pulse-width modulated control signal, and wherein the operation control parameter is a duty for the pulse width modulation.

2. The microcomputer according to claim 1 ,
wherein the communication interface writes a correction time to the second register,
wherein the correction time is supplied to the communication interface via the network and specifies the time to update the operation control parameter value from the current value to the update value, and
wherein the parameter update program calculates the update value to be used as the operation control parameter value at the correction time.

3. The microcomputer according to claim 2 ,
wherein the communication interface includes a first buffer that is capable of holding at least one piece of data and outputs held data in the same order as the data was input, and
wherein the communication interface writes the correction time to the first buffer, compares a value held in the first register with a value held in the second register and, if a match is found, writes an output from the first buffer to the second register.

4. The microcomputer according to claim 2 ,
wherein the peripheral module interrupt is coupled to the peripheral module via an interrupt selection circuit.

5. The microcomputer according to claim 2 ,
wherein the peripheral module interrupt is directly coupled to the peripheral module,
wherein the peripheral module includes a PWM generator circuit and the fourth register and includes a second buffer capable of holding at least one piece of data and outputting held data in the same order as the data was input, and
wherein the PWM generator circuit generates the pulse-width modulated control signal based on the current value held in the third register and transfers a value output from the second buffer to the third register when the peripheral module interrupt is input.

6. The microcomputer according to claim 5 ,
wherein the PWM generator circuit generates a 3-phase control signal,
wherein the peripheral module further includes a variable delay circuit, a phase adjustment circuit, and a phase register,
wherein the variable delay circuit is inserted correspondingly to the 3-phase control signal,
wherein the phase adjustment circuit supplies a delay amount to the variable delay circuit, and
wherein the phase register supplies a phase adjustment parameter to the phase adjustment circuit.

7. The microcomputer according to claim 1 ,
wherein the peripheral module generates the pulse-width modulated control signal to control an externally coupled device,
wherein the communication interface writes a start time and a correction time to the second register,
wherein the start time is supplied to the communication interface via the network,
wherein the correction time specifies the time to update the operation control parameter value from the current value to the update value, and
wherein the parameter update program includes a step that writes an initial value of the operation control parameter to the third register at the start time, permits the peripheral module interrupt in response to the CPU interrupt at the start time, and inhibits a subsequent CPU interrupt.

8. The microcomputer according to claim 7 ,
wherein the peripheral module generates a plurality of pulse-width modulated control signals to control a plurality of externally coupled devices,
wherein the operation control parameter value for each device is a duty for the pulse width modulation of the corresponding pulse-width modulated control signal,
wherein the communication interface includes a plurality of the second registers corresponding to control signals and writes a corresponding start time and a corresponding correction time to each of the second registers,
wherein the start time and the correction time are supplied to the communication interface via the network,
wherein the comparison circuit compares a value held in the first register with values held in the second registers and, if a match is found, issues a plurality of peripheral module interrupts corresponding to the control signals to the peripheral module,
wherein the peripheral module includes a plurality of the third registers and the fourth registers corresponding to the control signals and generates the control signals based on the corresponding current values of the operation control parameter, and
wherein the peripheral module transfers values stored in the fourth registers to the corresponding third registers in response to the corresponding peripheral module interrupts.

Assignees

• Renesas Electronics Corp

Inventors

• Suzuki Shinichi
• Takitsune Yuichi

Classifications

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F1/00

  Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00 (architectures of general purpose stored program computers G06F15/76) · CPC title

• G06F7/00

  Methods or arrangements for processing data by operating upon the order or content of the data handled (logic circuits H03K19/00) · CPC title