Systems and methods for protection of reflective memory systems

Patent metadata

Field	Value
Publication number	US-9928181-B2
Application number	US-201414550143-A
Country	US
Kind code	B2
Filing date	Nov 21, 2014
Priority date	Nov 21, 2014
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

A computing device within a reflective memory system includes a memory block and a special purpose processor. The memory block includes a plurality of memory areas, which are configured to store data of a corresponding one of a plurality of external devices. The special purpose processor is configured to intercept a write request. The write request is associated with a first external device of the plurality of external devices, and the first external device is associated with a first memory area of the plurality of memory areas. The special purpose processor is configured to determine whether the write request is valid or invalid, write the data of the first external device to the first memory area if the write request is valid, and prevent the data of the first external device from being written to the memory block if the write request is invalid.

First claim

What is claimed:

1. A computing device within a reflective memory system, the computing device comprising:
a memory block including a plurality of memory areas, each of the plurality of memory areas being configured to store data of a corresponding one of a plurality of external devices; and
a processor configured to,
intercept a write request, the write request being associated with a first external device of the plurality of external devices, the first external device being associated with a first memory area of the plurality of memory areas,
determine whether the write request is valid,
write the data of the first external device to the first memory area if the determining determines that the write request is valid;

the processor further configured to,
initiate a data refresh timer based on intercepting the write request, and
trigger a safety system based on a determination that the data refresh timer has expired prior to the data of the first external device being written to the first memory area, such that the writing the data of the first external device to the first memory area is ongoing concurrently with the data refresh timer being expired.

2. The computing device of claim 1 , wherein in the determining, the processor is configured to:
determine that the write request is valid if the write request indicates to write data of the first external device to the first memory area, and
determine that the write request is invalid if the write request indicates to write data of the first external device to another one of the plurality of memory areas.

3. The computing device of claim 2 , wherein the processor is further configured to:
prevent the data of the first external device from being written to the first memory area if the determining determines that the write request is invalid.

4. The computing device of claim 2 , wherein the processor is further configured to:
transmit a second write request to a second computing device within the reflective memory system,
the second computing device including,
a second memory block including a second plurality of memory areas, each of the second plurality of memory areas being configured to store data of corresponding ones of the plurality of external devices, and
a second processor configured to,
intercept the second write request,
determine whether the second write request is valid, and
write the data of the first external device to a first memory area of the second plurality of memory areas if the determining determines that the second write request is valid.

5. The computing device of claim 4 , wherein the first memory area of the second plurality of memory areas having a same memory address as the first memory area of the plurality of memory areas.

6. The computing device of claim 1 , wherein the computing device further comprises:
a separate processor, and in the intercepting, the processor is configured to obtain the write request from the separate processor.

7. The computing device of claim 6 , wherein the computing device further comprises:
a network interface, the computing device is connected to the first external device via the network interface, and the separate processor issues the write request based on data received from the first external device.

8. The computing device of claim 6 , wherein the computing device further comprises:
a network interface, and in the intercepting, the processor is configured to obtain the write request from another computing device within the reflective memory system via the network interface.

9. The computing device of claim 8 , wherein the separate processor is configured to:
obtain a read request from the other computing device, the read request indicating to read data from at least one of the plurality of memory areas; and
provide the data to the other computing device according to the obtained read request.

10. A method for writing data to a designated one of a plurality of memory areas in a memory block of a computing device within a reflective memory system, each of the plurality of memory areas being configured to store data of a corresponding one of a plurality of external devices, the method comprising:
intercepting, by a processor, a write request, the write request being associated with a first external device of the plurality of external devices, the first external device being associated with a first memory area of the plurality of memory areas;
determining, by the processor, whether the write request is valid;
writing, by the processor, the data of the first external device to a designated memory area if the determining determines that the write request is valid;
initiating a data refresh timer based on intercepting the write request; and
triggering a safety system based on a determination that the data refresh timer has expired prior to the data of the first external device being written to the first memory area, such that the writing the data of the first external device to the first memory area is ongoing concurrently with the data refresh timer being expired.

11. The method of claim 10 , wherein the determining comprises:
determining that the write request is valid if the write request indicates to write data of the first external device to the designated memory area; and
determining that the write request is invalid if the write request indicates to write data of the first external device to another one of the plurality of memory areas.

12. The method of claim 11 , further comprising:
preventing the data of the first external device from being written to the first memory area if the determining determines that the write request is invalid.

13. The method of claim 11 , further comprising:
transmitting a second write request to a second computing device within the reflective memory system, the second computing device including a second memory block including a second plurality of memory areas, each of the second plurality of memory areas being configured to store the data of the corresponding ones of the plurality of external devices, and
the second write request indicating to write the data of the first external device to a first memory area of the second plurality of memory areas if a second processor of the second computing device determines that the second write request is valid.

14. The method of claim 13 , wherein the first memory area of the second plurality of memory areas has a same memory address as the first memory area of the plurality of memory areas.

15. The method of claim 10 , wherein the intercepting comprises:
obtaining, by the processor, the write request from a separate processor, the separate processor issuing the write request based on data received from the first external device.

16. The method of claim 15 , wherein the intercepting comprises:
obtaining, by the processor, the write request from another computing device within the reflective memory system.

17. The method of claim 16 , wherein,
the separate processor obtains a read request from the other computing device, the read request indicating to read data from at least one of the plurality of memory areas; and
the separate processor provides the data to the other computing device according to the obtained read request.

18. A reflective memory system comprising:
a first computing device including,
a first memory block including a first plurality of memory areas, each of the first plurality of memory areas being configured to store data of a corresponding one of a plurality of external devices, and
a first pr

Assignees

• Meek Oscar L
• Droba Gregory S
• Ge Hitachi Nuclear Energy Americas Llc

Inventors

• Meek Oscar L
• Droba Gregory S

Classifications

• G06F11/20

  using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements · CPC title

• G06F2212/1052

  Security improvement · CPC title

• G06F11/1666

  where the redundant component is memory or memory area · CPC title

• G06F11/0796

  Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element · CPC title

• G06F11/0751 Primary

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title