Cache replacement policy

Patent metadata

Field	Value
Publication number	US-9928179-B2
Application number	US-201114385968-A
Country	US
Kind code	B2
Filing date	Dec 16, 2011
Priority date	Dec 16, 2011
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

Cache replacement policy. In accordance with a first embodiment of the present invention, an apparatus comprises a queue memory structure configured to queue cache requests that miss a second cache after missing a first cache. The apparatus comprises additional memory associated with the queue memory structure is configured to record an evict way of the cache requests for the cache. The apparatus may be further configured to lock the evict way recorded in the additional memory, for example, to prevent reuse of the evict way. The apparatus may be further configured to unlock the evict way responsive to a fill from the second cache to the cache. The additional memory may be a component of a higher level cache.

First claim

What is claimed is:

1. An apparatus comprising:
a queue memory structure to queue cache requests that miss a second cache after missing a first cache; and
additional memory associated with said queue memory structure to record an evict way of said cache requests for said first cache, wherein the evict way is a location in said first cache that serves as a destination for evicted data, wherein the apparatus is configured to lock said evict way recorded in said additional memory, wherein said locking prevents the evict way located in said first cache from being evicted.

2. The apparatus of claim 1 further to unlock said evict way responsive to a fill from said second cache to said first cache.

3. The apparatus of claim 1 wherein said second cache is inclusive of said first cache.

4. The apparatus of claim 1 further comprising:
a third memory structure to record pseudo least recently used information of said first cache; and
wherein said third memory structure is to be accessed by said first cache and said second cache.

5. The apparatus of claim 1 wherein said first cache is a Level 1 Data cache.

6. The apparatus of claim 5 wherein said second cache is a Level 2 cache.

7. A method comprising:
receiving a lookup request at a first cache;
responsive to a miss of said request at said first cache, forwarding said request to a second cache, wherein said second cache is at a higher level of a memory hierarchy than said first cache;
responsive to a miss of said request at said second cache, forwarding said request to a second cache miss queue;
determining an evict way for said first cache corresponding to said request;
storing said evict way in said second cache miss queue, wherein the evict way is a location in said first cache that serves as a destination for evicted data; and
locking said evict way, wherein said locking prevents the evict way located in said first cache from being evicted.

8. The method of claim 7 wherein said determining occurs in a same clock cycle said forwarding said request to said second cache.

9. The method of claim 7 further comprising: unlocking said evict way responsive to filling said request from said second cache.

10. The method of claim 7 wherein said determining further comprises determining said evict way in accordance with a pseudo least recently used cache replacement policy.

11. The method of claim 7 wherein said first cache is a Level 1 Data cache.

12. The method of claim 7 wherein said second cache is a Level 2 cache.

13. The method of claim 7 wherein said second cache is inclusive of said first cache.

14. A computer system comprising:
a cache subsystem to choose an evict way for a missed request to a first level cache on the same clock cycle that said request accesses a next higher level of memory; and
additional memory associated with said cache subsystem to record an evict way of said missed request for said first cache, wherein the evict way is a location in said first cache that serves as a destination for evicted data
wherein the computer system is configured to lock said evict way recorded in said additional memory, wherein said locking prevents the evict way located in said first cache from being evicted.

15. The computer system of claim 14 wherein said next higher level of memory is a cache memory structure.

16. The computer system of claim 15 wherein said cache memory structure is inclusive of said first cache.

17. The computer system of claim 14 further to choose said evict way in accordance with a pseudo least recently used cache replacement policy.

Assignees

• Avudaiyappan Karthikeyan
• Abdallah Mohammad
• Intel Corp

Inventors

• Avudaiyappan Karthikeyan
• Abdallah Mohammad

Classifications

• G06F12/0859

  with reload from main memory · CPC title

• G06F2212/251

  Local memory within processor subsystem · CPC title

• G06F12/124

  being minimized, e.g. non MRU · CPC title

• G06F12/126

  with special data handling, e.g. priority of data or instructions, handling errors or pinning · CPC title

• G06F12/0897 Primary

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title