Leveling stress factors among like components in a server

Patent metadata

Field	Value
Publication number	US-9928154-B2
Application number	US-201614993530-A
Country	US
Kind code	B2
Filing date	Jan 12, 2016
Priority date	Jan 12, 2016
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

A method and computer program product for causing a processor to perform the method are provided. The method includes monitoring a plurality of operating parameters for each of multiple components of a compute node, wherein the multiple components have the same component type, and determining a stress factor score for each of the multiple components, wherein the stress factor score is a function of the plurality of operating parameters. The method further includes reducing use of a first component from among the multiple components, wherein the first component has a stress factor score that is greater than the stress factor score for any of the other components of the same component type. Optionally, the method may prioritize use of each of the multiple components in an order of ascending stress factor score.

First claim

What is claimed is:

1. A method, comprising:
monitoring a plurality of operating parameters for each of multiple memory modules of a compute node;
determining a stress factor score for each of the multiple memory modules, wherein the stress factor score is a function of the plurality of operating parameters; and
reducing use of a first memory module relative to other memory modules within the compute node including reprogramming a memory channel configuration within the compute node to change an order in which memory channels are used, wherein the stress factor score determined for the first memory module is greater than the stress factor score determined for any of the other memory modules.

2. The method of claim 1 , further comprising:
increasing use of a second memory module from among the multiple memory modules, wherein the stress factor score determined for the second memory module is less than the stress factor score for any of the other memory modules.

3. The method of claim 1 , further comprising:
prioritizing use of each of the multiple memory modules in an order of ascending stress factor score determined for the respective one of the memory modules.

4. The method of claim 1 , wherein reducing use of the first memory module from among the multiple memory modules includes placing the first memory module in an idle state.

5. The method of claim 1 , wherein the plurality of operating parameters are selected from on/off cycles, thermal average, read/write cycles, usage time, correctable error count, uncorrectable error count, memory training time during power-on self-test, and memory training error count during power-on self-test.

6. The method of claim 1 , wherein the stress factor score determined for each of the multiple memory modules is a cumulative total number of occurrences of one or more event types.

7. The method of claim 6 , wherein the stress factor score determined for each of the multiple memory modules is determined by weighting a cumulative total number of occurrences of a first event type differently than a cumulative total number of occurrences of a second event type.

8. The method of claim 1 , wherein each of the multiple memory modules is a pluggable memory module.

9. The method of claim 1 , wherein the plurality of operating parameters are selected from power on time, power on/off cycles, and memory speed.

10. The method of claim 9 , wherein the plurality of operating parameters are monitored by an operating system of the compute node.

11. The method of claim 1 , wherein a first memory channel including the first memory module is moved down in an order of memory channel usage.

12. The method of claim 1 , wherein reducing use of the first memory module relative to the other memory modules within the compute node includes removing the first memory module from use.

13. The method of claim 12 , further comprising:
putting the first memory module back in use only in response to failure of one of the other memory modules.

14. The method of claim 1 , further comprising:
periodically determining and writing an updated value of the stress factor score for each of the multiple memory modules to non-volatile memory on a respective one of the memory modules.

15. The method of claim 14 , wherein the updated value of the stress factor score for each of the multiple memory modules is equal to a stress factor score previously stored in the non-volatile memory on the respective one of the multiple memory modules plus a stress factor score accumulated since the previously stored stress factor score for the respective one of the multiple memory modules.

16. A computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions being executable by a processor to cause the processor to:
monitor a plurality of operating parameters for each of multiple memory modules of a compute node;
determine a stress factor score for each of the multiple memory modules, wherein the stress factor score is a function of the plurality of operating parameters; and
reduce use of a first memory module relative to other memory modules within the compute node including reprogramming a memory channel configuration within the compute node to change an order in which memory channels are used, wherein the stress factor score determined for the first memory module is greater than the stress factor score determined for any of the other memory modules.

17. The computer program product of claim 16 , the program instructions being executable by the processor to further cause the processor to:
increase use of a second memory module from among the multiple memory modules, wherein the stress factor score determined for the second memory module is less than the stress factor score for any of the other memory modules.

18. The computer program product of claim 16 , the program instructions being executable by the processor to further cause the processor to:
prioritize use of each of the multiple memory modules in an order of ascending stress factor score determined for the respective one of the memory modules.

19. The computer program product of claim 16 , wherein the plurality of operating parameters are selected from power on time, power on/off cycles, and memory speed.

20. The computer program product of claim 16 , wherein a first memory channel including the first memory module is moved down in an order of memory channel usage.

Assignees

• Lenovo Entpr Solutions Singapore Pte Ltd

Inventors

• Kangas Paul D
• Ranck Daniel M

Classifications

• G06F11/3495 Primary

  for systems · CPC title

• G06F11/008

  Reliability or availability analysis · CPC title

• G06F9/505 Primary

  considering the load · CPC title