System and method for testing a logic-based processing device

Patent metadata

Field	Value
Publication number	US-9928150-B2
Application number	US-201414318976-A
Country	US
Kind code	B2
Filing date	Jun 30, 2014
Priority date	Jun 30, 2014
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

A method of operating a test device for a logic-based processing device includes the steps of providing an original set of test instructions, generating one or more Quick Error Detection (QED) test programs, and causing the one or more QED test programs to be executed on the logic-based processing device. Each one of the QED test programs includes the original test program with additional instructions inserted at strategic locations within the original set, wherein the additional instructions and the strategic locations vary between each of the QED test programs.

First claim

What is claimed is:

1. A method of operating a test device for a logic-based processing device comprising:
accessing an original test program;
generating a plurality of quick error detection (QED) test programs, each of the QED test programs including the original test program with additional instructions inserted at strategic locations within the original test program, wherein the additional instructions and the strategic locations vary between each of the QED test programs and the strategic locations of the additional instructions occur periodically in each one of the plurality of QED test programs, such that the number of instructions from the original test program between the strategic locations is the same for a given QED test program; and
storing the plurality of QED tests programs on a non-transitory memory for later execution by the logic-based processing device.

2. The method of claim 1 wherein the period of the strategic locations of the additional instructions is different for each one of the plurality of QED test programs.

3. The method of claim 2 wherein the number of instructions from the original test program between the strategic locations of the additional instructions for each one of the plurality of QED test programs are successive integers.

4. The method of claim 2 further comprising providing one or more test parameters, wherein the one or more test parameters are used to determine the period of the strategic locations of the additional instructions in each one of the plurality of QED test programs.

5. The method of claim 1 wherein the period of the strategic locations of the additional instructions in at least two of the plurality of QED test programs is the same.

6. The method of claim 1 wherein the plurality of QED test programs include at least:
a first QED test program; and
a second QED test program, wherein the strategic locations of the additional instructions in the first QED test program and the second QED test program occur at a first period.

7. The method of claim 6 wherein the plurality of QED test programs further include:
a third QED test program; and
a fourth QED test program, wherein the strategic locations of the additional instructions in the third QED test program and the fourth QED test program occur at a second period.

8. The method of claim 7 wherein the first period and the second period are successive integers.

9. The method of claim 7 wherein the plurality of QED test programs further include:
a fifth QED test program, wherein the strategic locations of the additional instructions in the fifth QED test program occur at the second period.

10. The method of claim 1 wherein the additional instructions:
duplicate each block of instructions in the original test program between the strategic locations; and
compare the result of each block of original test instructions between the strategic locations to the result of the duplicated instructions.

11. The method of claim 1 wherein the additional instructions check one or more values produced by the original test program against one or more expected values.

12. The method of claim 1 wherein the additional instructions:
assign each block of original test instructions between the strategic locations a unique signature;
construct a control flow graph indicating allowable transitions between the unique signatures; and
check if the unique signature of the currently executing block of original test instructions is a valid successor of the unique signature of the previously executed block of original test instructions based on the control flow graph.

13. The method of claim 1 wherein the additional instructions:
assign each block of original test instructions between the strategic locations a unique signature;
construct a control flow graph indicating allowable transitions between the unique signatures; and
on a separate thread from the QED test program, check if the unique signature of the currently executing block of original test instructions in the QED test program is a valid successor of the unique signature of the previously executed block of original test instructions in the QED test program based on the control flow graph.

14. The method of claim 1 wherein the additional instructions:
assign each block of original test instructions between the strategic locations a unique signature; and
save the unique signature of the currently executing block of original test instructions.

15. A test device for a logic-based processing device comprising:
a general purpose processor; and
a non-transitory memory, the non-transitory memory including:
an original set of test instructions; and
instructions configured to cause the general purpose processor to generate a plurality of quick error detection (QED) test programs, each of the QED test programs including the original set of test instructions with additional instructions inserted at strategic locations within the original set, wherein the strategic locations vary between each of the QED test programs and the strategic locations of the additional instructions occur periodically in each one of the plurality of QED test programs.

16. The test device of claim 15 wherein the period of the strategic locations of the additional instructions is different for each one of the plurality of QED test programs.

17. The test device of claim 16 wherein the period of the strategic locations of the additional instructions for each one of the plurality of QED test programs are successive integers.

18. The test device of claim 16 further comprising providing one or more test parameters, wherein the one or more test parameters are used to determine the period of the strategic locations of the additional instructions in each one of the plurality of QED test programs.

19. The test device of claim 15 wherein the period of the strategic locations of the additional instructions in at least two of the plurality of QED test programs is the same.

20. The test device of claim 15 wherein the plurality of QED test programs include at least:
a first QED test program; and
a second QED test program, wherein the strategic locations of the additional instructions in the first QED test program and the second QED test program occur at a first period.

21. The test device of claim 20 wherein the plurality of QED test programs further include:
a third QED test program; and
a fourth QED test program, wherein the strategic locations of the additional instructions in the third QED test program and the fourth QED test program occur at a second period.

22. The test device of claim 21 wherein the first period and the second period are successive integers.

23. The test device of claim 21 wherein the plurality of QED test programs further include:
a fifth QED test program, wherein the strategic locations of the additional instructions in the fifth QED test program occur at the second period.

24. The test device of claim 15 wherein the additional instructions:
duplicate each block of instructions in the original test program between the strategic locations; and
compare the result of each block of original test instructions between the strategic locations to the result of the duplicated instructions.

25. The test device of claim 15 wherein the additional instructions check one or more values produced by the original test program against one or more expected values.

Assignees

• Univ Leland Stanford Junior

Inventors

• Lin Hai
• Mitra Subhasish

Classifications

• G06F11/2236 Primary

  to test CPU or processors · CPC title

• G06F11/263

  Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers} · CPC title