Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9927993-B2
Application number	US-201615286751-A
Country	US
Kind code	B2
Filing date	Oct 6, 2016
Priority date	Mar 14, 2016
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

A semiconductor memory device includes a memory cell array including a block of memory cells, gates of which are connected to a plurality of word lines, and a control unit configured to perform a writing operation in response to a command received from the outside, the writing operation including applying a program level voltage to at least two word lines at the same time.

First claim

What is claimed is:

1. A method of performing dummy data writing on a block of memory cells of a semiconductor memory device, comprising:
incrementing a count value for the block each time data is read from the block, the count value for the block being reset when all word lines of the block have been used; and
issuing a command to perform data writing with dummy data when the count value reaches a threshold value.

2. The method according to claim 1 , wherein the dummy data to be written pursuant to the command is supplied to the semiconductor memory device.

3. The method according to claim 1 , wherein the dummy data to be written pursuant to the command is not supplied to the semiconductor memory device.

4. The method according to claim 1 , wherein the command specifies an address where the data writing with the dummy data is to begin.

5. The method according to claim 1 , wherein
when the count value reaches the threshold value, multiple commands are issued, each of the commands specifying a different address where the data writing with the dummy data is to begin.

6. A memory system, comprising:
a memory cell array including a block of memory cells, gates of which are connected to a plurality of word lines;
a controller configured to increment a count value for the block each time data is read from the block, the count value for the block being reset when all word lines of the block have been used, and issue a command to perform data writing with dummy data when the count value reaches a threshold value.

7. The semiconductor memory device according to claim 6 , wherein the controller specifies the dummy data to be written pursuant to the command.

8. The semiconductor memory device according to claim 6 , wherein the controller does not specify the dummy data to be written pursuant to the command.

9. The semiconductor memory device according to claim 6 , wherein the command specifies an address where the data writing with the dummy data is to begin.

10. The semiconductor memory device according to claim 6 , wherein
when the count value reaches the threshold value, the controller issues multiple commands, each specifying a different address where the data writing with the dummy data is to begin.

Assignees

• Toshiba Memory Corp

Inventors

• Ochi Yusuke
• Shirakawa Masanobu

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G06F2212/205

  Hybrid memory, e.g. using both volatile and non-volatile memory · CPC title

• G11C16/10

  Programming or data input circuits · CPC title