Method of dynamic table journaling

Patent metadata

Field	Value
Publication number	US-9927985-B2
Application number	US-201615167738-A
Country	US
Kind code	B2
Filing date	May 27, 2016
Priority date	Feb 18, 2016
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

Embodiments of the disclosure are directed to a journaling scheme in a flash memory device. Advantageously, embodiments described can be used to keep the rebuild time of a Flash Translation Layer (FTL) mapping table to a maximum upon restart from a sudden power-loss event.

First claim

What is claimed is:

1. A non-volatile memory (NVM) controller configured to:
receive a command from a host device;
upon receiving the command, update an estimated rebuild time, the estimated rebuild time associated with rebuilding a logical-address-to-physical-address mapping table on restart from an event, the updated estimated rebuild time based on at least:
a copy time associated with copying information stored in a second logical-address-to-physical-address mapping table to the logical-address-to-physical-address mapping table; and
a replay time of a plurality of commands, the plurality of commands including the command;

determine that the updated estimated rebuild time exceeds a threshold value;
trigger a journaling event based on the determination, wherein the journaling event updates a portion of the second logical-address-to-physical address mapping table; and
reduce the updated estimated rebuild time based on the journaling event.

2. The non-volatile memory controller of claim 1 wherein the reduction in the estimated rebuild time corresponds to the replay time of a journal interval following the restart from the event.

3. The non-volatile memory controller of claim 1 , wherein the controller is further configured to determine that the reduced updated estimated rebuild time is below the threshold value.

4. The non-volatile memory controller of claim 1 wherein the logical-address-to-physical-address mapping table and the second logical-address-to-physical-address mapping table are associated with a flash translation layer.

5. The non-volatile memory controller of claim 1 wherein the plurality of commands comprise a plurality of trim commands.

6. The non-volatile memory controller of claim 1 wherein the second logical-address-to-physical-address mapping table is located in a non-volatile memory.

7. The non-volatile memory controller of claim 6 wherein the rebuilding is further based on physical to logical mapping data in the non-volatile memory and the rebuilding is further based on recovery data in a system area of the non-volatile memory.

8. The non-volatile memory controller of claim 1 wherein the event is a sudden power loss event.

9. The non-volatile memory controller of claim 6 wherein the logical-address-to-physical-address mapping table is located in a volatile memory accessible to the non-volatile memory.

10. The non-volatile memory controller of claim 1 wherein the portion of the second logical-address-to-physical address mapping table updated by the journaling event is a segment of the second logical-address-to-physical-address mapping table.

11. The non-volatile memory controller of claim 1 wherein the threshold value is related to the maximum permissible rebuild time to meet a specification.

12. A method comprising:
receiving a command from a host device;
upon receiving the command, updating an estimated rebuild time, the estimated rebuild time associated with rebuilding a logical-address-to-physical-address mapping table on restart from an event, the updated estimated rebuild time based on at least:
a copy time associated with copying information stored in a second logical-address-to-physical-address mapping table to the logical-address-to-physical-address mapping table; and
a replay time of a plurality of commands, the plurality of commands including the command;

determining that the updated estimated rebuild time exceeds a threshold value;
triggering a journaling event based on the determination, wherein the journaling event updates a portion of the second logical-address-to-physical address mapping table; and
reducing the updated estimated rebuild time based on the journaling event.

13. The method of claim 12 wherein the reduction in the estimated rebuild time corresponds to the replay time of a journal interval following the restart from the event.

14. The method of claim 12 further comprising determining that the reduced updated estimated rebuild time is below the threshold value.

15. The method of claim 12 wherein the logical-address-to-physical-address mapping table and the second logical-address-to-physical-address mapping table are associated with a flash translation layer.

16. The method of claim 12 wherein the plurality of commands comprise a plurality of trim commands.

17. The method of claim 12 wherein the second logical-address-to-physical-address mapping table is located in a non-volatile memory.

18. The method of claim 12 wherein the rebuilding is further based on physical to logical mapping data in the non-volatile memory and the rebuilding is further based on recovery data in a system area of the non-volatile memory.

19. The method of claim 18 wherein the event is a sudden power loss event.

20. The method of claim 12 wherein the logical-address-to-physical-address mapping table is located in a volatile memory accessible to the non-volatile memory.

21. The method of claim 18 wherein the portion of the second logical-address-to-physical address mapping table updated by the journaling event is a segment of the second logical-address-to-physical-address mapping table.

22. The method of claim 12 wherein the threshold value is related to the maximum permissible rebuild time to meet a specification.

Assignees

• Sk Hynix Inc

Inventors

• Zhang Fan
• Cai Yu

Classifications

• G06F11/1446

  Point-in-time backing up or restoration of persistent data · CPC title

• G06F11/1441

  Resetting or repowering · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title