Variable precision in hardware pipelines for power conservation

Patent metadata

Field	Value
Publication number	US-9927862-B2
Application number	US-201514718512-A
Country	US
Kind code	B2
Filing date	May 21, 2015
Priority date	May 21, 2015
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

A digital signal processor includes a variable precision hardware pipeline that provides a maximum level of precision using a first plurality of bits for a mathematical representation. The pipeline stages include data registers to store the first plurality of bits. A precision select module selects a level of precision for processing a block of instructions and sets a precision control register. Logic circuitry utilizes the precision control register to gate the clock signal for one or more of the first plurality of bits to reduce the precision of the hardware pipeline. The logic circuitry disables the clock signal for the data latches in the pipeline corresponding to bits to be disabled to reduce the precision. By disabling the clock signal for the data registers, the amount of power consumed by the pipeline can be reduced.

First claim

What is claimed is:

1. A digital signal processing system, comprising:
a hardware pipeline including a clock signal and a set of data latches for storing a first plurality of bits in a first pipeline stage;
a control register configured to select a precision of the hardware pipeline;
control logic configured to determine for a data frame that a first precision of the hardware pipeline can be used when processing a first segment of the data frame and a second precision that is lower than the first precision can be used when processing a second segment of the data frame, the control logic is configured to set the control register to select the first precision of the hardware pipeline for the first segment and the second precision for the second segment; and
one or more gates configured to disable the clock signal for a first number of the data latches of the hardware pipeline based on the control register when processing the first segment and a second number of data latches when processing the second segment, the first number is less than the second number.

2. The digital signal processing system of claim 1 , wherein:
the control register includes a plurality of precision bits corresponding to a subset of the first plurality of bits in the first pipeline stage; and
the one or more gates are configured to disable the clock signal for the first number of data latches of the hardware pipeline based on one or more of the precision bits corresponding to the first number of data latches.

3. The digital signal processing system of claim 1 , wherein:
the control register is configured to store a value indicating a number of the first plurality of bits for which the clock signal is to be disabled; and
the number of the first plurality of bits is a number of bits beginning with a least significant bit to be disabled.

4. The digital signal processing system of claim 1 , wherein:
the control logic is configured to predict for the plurality of data frames whether the full precision can be reduced without accessing the plurality of data frames.

5. The digital signal processing system of claim 1 , wherein:
the set of data latches is a first set of data latches;
the hardware pipeline includes one or more additional sets of data latches for storing the first plurality of bits in each of one or more additional pipeline stages of the hardware pipeline; and
the one or more gates are configured to disable the clock signal for a first number of the data latches in the one or more additional sets of data latches for the one or more additional pipeline stages during processing of the first segment.

6. The digital signal processing system of claim 1 , wherein:
the one or more data frames include a first data frame and a second data frame;
the hardware pipeline is configured to process the first data frame prior to the control logic predicting for the second data frame whether the full precision of the hardware pipeline can be reduced; and
the control logic is configured to predict that a full precision of the hardware pipeline can be reduced for the second data frame based on a correspondence between the first data frame and the second data frame.

7. A method of digital signal processing, comprising:
determining for a data frame that a first precision of a hardware pipeline can be used when processing a first segment of the data frame and a second precision that is lower than the first precision can be used when processing a second segment of the data frame, the hardware pipeline includes a set of data latches for storing a plurality of bits in a first pipeline stage of the hardware pipeline and a clock signal coupled to each of the data latches;
setting a precision configuration register to indicate the first precision for processing the first segment and the second precision for processing the second segment; and
in response to the precision configuration register, disabling the clock signal for a first number of the data latches in the first pipeline stage during processing of the first segment and a second number of the data latches during processing of the second segment of the data frame, wherein the first number is less than the second number.

8. The method of claim 7 , wherein:
said determining that the first precision and the second precision of the hardware pipeline can be used is performed without accessing the data frame; and
said determining that the first precision and the second precision of the hardware pipeline can be used is performed by a precision select module of a processor coupled to the hardware pipeline.

9. The method of claim 7 , wherein:
said setting the precision configuration register includes setting a first value in the precision configuration register prior to processing the first segment by the hardware pipeline and setting a second value in the precision configuration register prior to processing the second segment.

10. The method of claim 7 , wherein:
the set of data latches is a first set of data latches;
the hardware pipeline includes a second set of data latches for storing the plurality of bits in a second pipeline stage of the hardware pipeline;
the clock signal is coupled to each of the data latches of the second set of data latches; and
said method further comprises disabling the clock signal for a first number of the data latches in the second set of data latches for the second pipeline stage during processing of the first segment and a second number of the data latches in the second set of data latches for the second pipeline stage during processing of the second segment.

11. The method of claim 7 , wherein the data frame is a second digital image frame, the method further comprising:
processing a first digital image frame prior to said determining for the second digital frame that the first precision and the second precision can be used; and
based on said processing the first digital image frame, determining that the first precision can be used for a first segment of the first digital image frame and a second precision can be used for a second segment of the first digital image frame; and
wherein said determining for the second digital image frame that the first precision can be used for the first segment and the second precision can be used for the second segment is based on a correspondence between the first segment of the first digital image frame and the first segment of the second digital image frame and a correspondence between the second segment of the first digital image frame and the second segment of the second digital image frame.

12. The method of claim 7 , wherein:
the precision configuration register includes a plurality of precision bits corresponding to a subset of the set of data latches; and
said disabling the clock signal includes disabling the clock signal for the first number of data latches of the hardware pipeline based on one or more of the precision bits corresponding to the first number of data latches.

13. An apparatus, comprising:
one or more hardware compute stages supporting a maximum precision;
one or more control circuits in communication with the one or more hardware compute stages, the one or more control circuits are configured to predict for one or more segments of a second data frame that a level of precision of the one or more compute stages can be reduced when processing the one or more segments based on a correspondence with one or more segments of a previously processed first data frame, the one or more control circuits are configured to disable at least a portion of the one or more hardware compute stages when processing the one or more segments of the seco

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Shearer Robert
• Tubbs Matthew
• Haraden Ryan

Classifications

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F1/3237 Primary

  by disabling clock generation or distribution · CPC title