Internal communication interconnect scalability

Patent metadata

Field	Value
Publication number	US-9927859-B2
Application number	US-201615175741-A
Country	US
Kind code	B2
Filing date	Jun 7, 2016
Priority date	Mar 11, 2013
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

Interconnect frequency control technologies of adjusting an operating frequency of a communication interconnect between an integrated circuit comprising multiple functional hardware units are described. A power management unit (PMU) is configured to collect workload data from the functional hardware units and determine a workload metric from the workload data. The PMU adjusts an operating frequency of the communication interconnect in view of the workload metric.

First claim

What is claimed is:

1. An integrated circuit comprising:
a communication interconnect;
a plurality of functional hardware units coupled to the communication interconnect; and
a power management unit (PMU) coupled to the plurality of functional hardware units and the communication interconnect, wherein the PMU comprises an interconnect frequency controller to:
collect workload data from the plurality of functional hardware units;
collect system configuration information including a power state of the integrated circuit, a number of processor cores, a number of cache elements, and a number of threads;
determine a workload metric from the workload data and the system configuration information; and
adjust an operating frequency of the communication interconnect up or down, in view of the workload metric, to an adjusted operating frequency, and

wherein, in response to the adjusted operating frequency of the communication interconnect, the PMU is further to adjust a frequency of a cache element of the cache elements to within a power envelope created by the adjusted operating frequency.

2. The integrated circuit of claim 1 , further comprising a phase-locked loop (PLL) coupled to the PMU, wherein the PLL is to receive an input from the PMU to set the operating frequency of the communication interconnect, and wherein the PMU is to adjust the operating frequency by changing the input of the PLL.

3. The integrated circuit of claim 1 , wherein, when the interconnect frequency controller adjusts the operating frequency of the communication interconnect up, the PMU is to lower the frequency of the cache element within the power envelope.

4. The integrated circuit of claim 1 , wherein, when the interconnect frequency controller adjusts the operating frequency of the communication interconnect down, the PMU is to increase the frequency of the cache element within the power envelope.

5. The integrated circuit of claim 1 , wherein the plurality of functional hardware units comprises:
the cache elements coupled to the communication interconnect;
a computation element coupled to the communication interconnect;
a memory connection coupled to the communication interconnect; and
the processor cores.

6. The integrated circuit of claim 5 , wherein the interconnect frequency controller is further to at least one of:
collect core data from the processor cores for the workload data;
collect cache element data from the cache elements for the workload data;
collect computation element data from the computation element for the workload data;
collect memory connection data from the memory connection for the workload data; or
collect communication interconnect data from the communication interconnect.

7. The integrated circuit of claim 1 , wherein the workload data comprises at least one of a pending queue size, a number of stalls waiting for the communication interconnect, or a latency.

8. The integrated circuit of claim 1 , wherein the interconnect frequency controller is further to compare the workload metric against a first threshold and a second threshold, and to increase the operating frequency when the workload metric exceeds the first threshold and to decrease the operating frequency when the workload metric exceeds the second threshold.

9. The integrated circuit of claim 1 , wherein, to adjust the operating frequency of the communication interconnect, the interconnect frequency controller is to set the operating frequency to one of a fixed multiple of the frequency or to a highest of available frequencies of the cache element.

10. The integrated circuit of claim 1 , wherein the interconnect frequency controller is further to:
predict system performance in view of the workload metric at a plurality of operating frequencies; and
select the operating frequency from among the plurality of operating frequencies to moderate power consumption of the communication interconnect in view of a predicted system performance at the operating frequency.

11. A method comprising:
collecting, by a power management unit (PMU), workload data from a plurality of functional hardware units coupled together via a communication interconnect;
collecting, by the PMU, system configuration information including a power state of an integrated circuit in which the plurality of functional hardware unit reside, a number of processor cores, a number of cache elements, and a number of threads;
determining, by the PMU, a workload metric from the workload data and the system configuration;
adjusting, by the PMU, an operating frequency of the communication interconnect up or down, in view of the workload metric, to an adjusted operating frequency; and
adjusting, by the PMU in response to the adjusted operating frequency of the communication interconnect, a frequency of a cache element of the cache elements to within a power envelope created by the adjusted operating frequency.

12. The method of claim 11 , wherein adjusting the operating frequency comprises changing an input of a phase-locked loop (PLL) that sets the operating frequency of the communication interconnect.

13. The method of claim 11 , wherein, when adjusting the operating frequency of the communication interconnect up, the method comprises lowering the frequency of the cache element within the power envelope.

14. The method of claim 11 , wherein, when adjusting the operating frequency of the communication interconnect down, the method comprises increasing the frequency of the cache element within the power envelope.

15. The method of claim 11 , wherein the collecting comprises at least one of:
collecting core data from the processor cores for the workload data;
collecting cache element data from the cache elements for the workload data;
collecting computation element data from a computation element for the workload data;
collecting memory connection data from a memory connection for the workload data; or
collecting communication interconnect data from the communication interconnect.

16. The method of claim 11 , wherein the workload data comprises at least one of a pending queue size, a number of stalls waiting for the communication interconnect, or a latency.

17. The method of claim 11 , further comprising:
comparing the workload metric against a first threshold and a second threshold;
increasing the operating frequency when the workload metric exceeds the first threshold; and
decreasing the operating frequency when the workload metric exceeds the second threshold.

18. The method of claim 11 , wherein adjusting the operating frequency of the communication interconnect comprises setting the operating frequency to one of a fixed multiple of the frequency or to a highest of available frequencies of the cache element.

19. The method of claim 11 , further comprising:
predicting system performance in view of the workload metric at a plurality of operating frequencies; and
selecting the operating frequency from among the plurality of operating frequencies to moderate power consumption of the communication interconnect in view a predicted system performance at the operating frequency.

20. A non-transitory, computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to:
collect, by a power management unit (PMU), workload data from a plurality of functional hardware units coupled together via a communication interconnect;
collect, by the PMU, system configuration information including a power state of an integrated circu

Assignees

• Intel Corp

Inventors

• Rosenzweig Nir
• Bolotin Evgeny
• Satat Guy
• Salah Hisham Abu

Classifications

• H03K3/0315

  Ring oscillators · CPC title

• G06F1/3203 Primary

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• Y02B60/1217

  Cross-Sectional Technologies · mapped topic

• H03L7/08

  Details of the phase-locked loop · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title