System and method for a linear voltage regulator

US9927828B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9927828-B2
Application numberUS-201514841476-A
CountryUS
Kind codeB2
Filing dateAug 31, 2015
Priority dateAug 31, 2015
Publication dateMar 27, 2018
Grant dateMar 27, 2018

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

According to an embodiment, a voltage regulator includes a linear voltage regulator (LVR) and a transient feedback circuit. The LVR a primary feedback loop, an input terminal configured to receive an input voltage, and an output terminal configured to output a regulated voltage. The transient feedback circuit is coupled to the output terminal and the primary feedback loop, and is configured to provide a first current with a first polarity to the primary feedback loop when current flowing through the output terminal is increasing.

First claim

Opening claim text (preview).

What is claimed is: 1. A voltage regulator comprising: a linear voltage regulator (LVR) comprising: an output transistor coupled between an input terminal and an output terminal, the output transistor having a gate coupled to a feedback node, a primary feedback loop comprising a first output feedback transistor having a gate coupled to the feedback node and a first conduction terminal coupled to a reference node, wherein the input terminal is configured to receive an input voltage, and the output terminal is configured to output a regulated voltage; a transient feedback circuit coupled to the output terminal and the primary feedback loop, wherein the transient feedback circuit is configured to increase a gate to source voltage of the output transistor when current flowing through the output terminal is increasing; and a current subtractor circuit coupled to the primary feedback loop and configured to stabilize voltage variations of the reference node by sinking current from the reference node when current flowing into the reference node increases. 2. The voltage regulator of claim 1 , wherein the current subtractor circuit comprises: a current mirror having a first branch and a second branch, the first branch coupled to the reference node; and a control transistor coupled to the second branch, wherein a control terminal of the control transistor is coupled to a control node of the primary feedback loop. 3. The voltage regulator of claim 1 , wherein the transient feedback circuit has a faster response time than the primary feedback loop. 4. The voltage regulator of claim 1 , wherein the transient feedback circuit comprises a first feedback capacitor coupled to the output terminal and a second feedback capacitor coupled to the output terminal. 5. The voltage regulator of claim 4 , wherein the first feedback capacitor and the second feedback capacitor each have a capacitance value less than or equal to 5 picofarads (pF). 6. The voltage regulator of claim 1 , wherein the transient feedback circuit comprises: a first feedback transistor coupled between a high supply line and the feedback node; a second feedback transistor coupled between a low supply line and the feedback node; a bias circuit coupled to the first feedback transistor and the second feedback transistor; and a capacitive differentiator circuit coupled to the output terminal and coupled to a control terminal of the first feedback transistor and a control terminal of the second feedback transistor. 7. The voltage regulator of claim 1 , wherein the transient feedback circuit comprises: a first feedback transistor coupled to the primary feedback loop; a second feedback transistor coupled to the first feedback transistor and a low supply line; a first bias circuit coupled to the first feedback transistor and the second feedback transistor; and a first feedback capacitor coupled to the output terminal and coupled to a control terminal of the second feedback transistor. 8. A voltage regulator comprising: a linear voltage regulator (LVR) comprising: a primary feedback loop, an input terminal configured to receive an input voltage, and an output terminal configured to output a regulated voltage; and a transient feedback circuit coupled to the output terminal and the primary feedback loop, wherein the transient feedback circuit is configured to provide a first current with a first polarity to the primary feedback loop when current flowing through the output terminal is increasing, wherein the transient feedback circuit comprises: a first feedback transistor coupled to the primary feedback loop, a second feedback transistor coupled to the first feedback transistor and a low supply line a first bias circuit coupled to the first feedback transistor and the second feedback transistor, a first feedback capacitor coupled to the output terminal and coupled to a control terminal of the second feedback transistor, a third feedback transistor coupled to the primary feedback loop, a fourth feedback transistor coupled to the third feedback transistor and a low supply line, a second bias circuit coupled to the third feedback transistor and the fourth feedback transistor, and a second feedback capacitor coupled to the output terminal and coupled to an intermediate node between the third feedback transistor and the fourth feedback transistor. 9. The voltage regulator of claim 1 , wherein: the primary feedback loop further comprises a current mirror having a first branch and a second branch, wherein the second branch is coupled to the feedback node; and the gate of the first output feedback transistor is coupled to a second conduction terminal of the first output feedback transistor. 10. The voltage regulator of claim 1 , wherein the primary feedback loop comprises a positive current feedback loop. 11. The voltage regulator of claim 1 , wherein no off-chip capacitor is coupled to the output terminal. 12. A method of generating a regulated output voltage, the method comprising: receiving an input voltage at an input terminal coupled to a first conduction terminal of an output transistor; generating the regulated output voltage at an output terminal coupled to a second conduction terminal of the output transistor, the output transistor having a gate coupled to a feedback node; regulating the regulated output voltage based on a reference voltage of a reference node using a primary feedback loop comprising a first output feedback transistor having a gate coupled to the feedback node and a first conduction terminal coupled to the reference node; increasing a gate to source voltage of the output transistor by using a transient feedback circuit coupled to the output terminal and the primary feedback loop when current flowing through the output terminal is increasing; and stabilizing voltage variations of the reference node by sinking current from the reference node with a current subtractor circuit when current flowing into the reference node increases. 13. The method of claim 12 , wherein the transient feedback circuit has a faster response time than the primary feedback loop. 14. The method of claim 12 , increasing the gate to source voltage of the output transistor comprises: generating a transient feedback control signal using a capacitive differentiator coupled to the output terminal; and regulating a transient feedback current that is coupled to the primary feedback loop based on the transient feedback control signal. 15. The method of claim 12 , wherein regulating the regulated output voltage using the primary feedback loop comprises positive current feedback that comprises: when current flowing through the output terminal is increasing: increasing a current flowing in the primary feedback loop, and increasing current flowing through the output terminal based on increasing the gate to source voltage of the output transistor; and when current flowing through the output terminal is decreasing: decreasing the current flowing in the primary feedback loop, decreasing the gate to source voltage of the output transistor based on decreasing the current flowing in the primary feedback loop, and decreasing current flowing through the output terminal based on decreasing the gate to source voltage of the output transistor. 16. The method of claim 12 , wherein no off-chip capacitor is coupled to the output terminal. 17. A voltage regulator comprising: a linear voltage regulator (LVR) comprising: an output transistor coupled between an input terminal and an output terminal, the output

Assignees

Inventors

Classifications

  • G05F3/267Primary

    using both bipolar and field-effect technology · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9927828B2 cover?
According to an embodiment, a voltage regulator includes a linear voltage regulator (LVR) and a transient feedback circuit. The LVR a primary feedback loop, an input terminal configured to receive an input voltage, and an output terminal configured to output a regulated voltage. The transient feedback circuit is coupled to the output terminal and the primary feedback loop, and is configured to …
Who is the assignee on this patent?
St Microelectronics Int Nv
What technology area does this patent fall under?
Primary CPC classification G05F3/267. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 27 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).