Accelerating and offloading lock access over a network
US-2016043965-A1 · Feb 11, 2016 · US
US9925492B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9925492-B2 |
| Application number | US-201514665043-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 23, 2015 |
| Priority date | Mar 24, 2014 |
| Publication date | Mar 27, 2018 |
| Grant date | Mar 27, 2018 |
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Remote transactions using transactional memory are carried out over a data network between an initiator host and a remote target. The transaction comprises a plurality of input-output (IO) operations between an initiator network interface controller and a target network interface controller. The IO operations are controlled by the initiator network interface controller and the target network interface controller to cause the first process to perform accesses to the memory location atomically.
Opening claim text (preview).
The invention claimed is: 1. A method of communication over a data network, comprising the steps of: performing a transaction across a data network between an initiator host and a remote target, the initiator host having an initiator network interface controller, and the remote target having a central processing unit including a first cache memory, a target network interface controller including a second cache memory, and a shared memory, wherein the shared memory is accessible by a first process and a second process, the transaction comprising a plurality of input-output (IO) operations between the initiator network interface controller and the target network interface controller, respectively; linking the first cache memory, the second cache memory and the shared memory by a coherent bus having bus lines; acquiring the coherent bus with the target network interface controller during the transaction and changing a status of the bus lines; and controlling the IO operations with the initiator network interface controller and the target network interface controller to cause the first process to perform accesses to the shared memory atomically with respect to the second process. 2. The method according to claim 1 , wherein the IO operations comprise messages including at least one of a first message to begin the transaction, a second message to commit the transaction and a third message that communicates a status of the transaction, further comprising responding to the messages with the target network interface controller. 3. The method according to claim 2 , wherein responding to the first message comprises causes a state transition of the transaction from an idle state to an active state. 4. The method according to claim 2 , wherein responding to the second message causes a state transition of the transaction from an active state to a committed state. 5. The method according to claim 2 , wherein responding to the messages comprises in the target network interface controller associating a set of read and write operations in the shared memory with the transaction. 6. The method according to claim 5 , wherein associating a set of read and write operations comprises: establishing a first table containing information on queue pairs of requester and responder processes that are participating in the transaction; and establishing a second table containing transaction resource information as chunks of data. 7. The method according to claim 6 , wherein a chunk comprises a cache line of the second cache memory and includes a reference to the first table, an address of the chunk, an identifier of valid bytes for the chunk, a read/write indicator of whether the chunk has been read or written by currently active transactions; a value to be committed in the transaction, and a pending-write indicator. 8. The method according to claim 2 , wherein responding to the messages comprises generating a status message with the target network interface controller to report the status of the transaction to the initiator network interface controller. 9. The method according to claim 1 , wherein contents of the shared memory are available to the first process and concealed from the second process until an occurrence of a final state of the transaction. 10. The method according to claim 1 , further comprising identifying accesses to the shared memory with the target network interface controller that conflict with the transaction. 11. The method according to claim 10 , further comprising the steps of: responsively to identifying accesses transmitting an abort message to the initiator network interface controller with the target network interface controller to cause the transaction to abort; and discarding results of store operations to the shared memory that occurred during the transaction. 12. The method according to claim 1 , wherein the IO operations are executed concurrently for a plurality of transactions. 13. The method according to claim 1 , wherein the remote target comprises a plurality of remote targets and the IO operations occur between the initiator network interface controller and selected ones of the remote targets. 14. The method according to claim 13 , wherein compute operations are performed responsively to the IO operations, and the compute operations are performed in the plurality of remote targets. 15. The method according to claim 1 , further comprising transmitting command messages from the initiator network interface controller to the target network interface controller, wherein the accesses to the shared memory are direct memory accesses that occur responsively to remote direct memory access requests in the command messages. 16. The method according to claim 1 , wherein compute operations are performed responsively to the IO operations, and the compute operations are performed only in the remote target. 17. A network communication apparatus, comprising: first circuitry comprising an initiator host interface linked to a coherent bus having bus lines, which is coupled to receive from an initiator host a request from an initiator process running on the initiator host to perform a transaction with a remote target via a data network, the remote target having a central processing unit including a first cache memory, a target network interface controller including a second cache memory, and a shared memory that is accessible by a first process and a second process, wherein the first cache memory, the second cache memory and the shared memory are linked to the coherent bus; and second circuitry comprising a host network interface controller coupled to the initiator host and the data network, the transaction comprising a plurality of input-output (IO) operations between the host network interface controller and the target network interface controller, the host network interface controller being configured for controlling the IO operations by controlling a status of the bus lines and by issuing commands to the target network interface controller to cause the first process to perform accesses to the shared memory atomically with respect to the second process. 18. The apparatus according to claim 17 , wherein the IO operations comprise messages including at least one of a first message to begin the transaction, a second message to commit the transaction and at least one third message that communicates a status of the transaction, wherein the host network interface controller is configured for responding to messages from the target network interface controller. 19. The apparatus according to claim 17 , wherein contents of the shared memory are available to the first process and concealed from the second process until an occurrence of a final state of the transaction. 20. The apparatus according to claim 17 , wherein the host network interface controller is configured for performing the IO operations for a plurality of transactions concurrently. 21. The apparatus according to claim 17 , wherein the remote target comprises a plurality of remote targets and the host network interface controller is configured for performing the IO operations with selected ones of the remote targets. 22. A network communication system, comprising: a remote target having a shared memory location that is accessible by a first process and a second process; first circuitry comprising a target network interface controller coupled to a data network; an initiator host having a central processing unit including a first cache
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