RDMA transfers in mapreduce frameworks

Patent metadata

Field	Value
Publication number	US-9923726-B2
Application number	US-201414559266-A
Country	US
Kind code	B2
Filing date	Dec 3, 2014
Priority date	Dec 3, 2014
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

Embodiments of the present invention provide methods, systems, and computer program products for transferring data in a MapReduce framework. In one embodiment, MapReduce jobs are performed such that data spills are stored by mapper systems in memory and are transferred to reducer systems via one-sided RDMA transfers, which can reduce CPU overhead of mapper systems and the latency of data transfer to reducer systems.

First claim

What is claimed is:

1. A method for transferring data in a MapReduce framework comprising a mapper system and a reducer system, the method comprising:
receiving, by one or more computer processors, a data split assigned to a mapper system;
registering, by one or more computer processors, a first fixed-address memory region for the mapper system to be used for a remote direct memory access (RDMA) reducer buffer, wherein the first fixed-address memory region is a locked memory region, expressed as a fixed memory address followed by a specified byte range, that is separated from dynamic memory regions on a virtual machine used by the mapper system, and wherein registering includes determining a size for the RDMA reducer buffer to be created based on a size of an RDMA mapper buffer of the mapper system to which the reducer system is assigned, wherein the RDMA reducer buffer is sized such that no data is spilled to disk;
executing, by one or more computer processors, one or more mapper tasks on the data split to generate output results;
spilling, by one or more computer processors, generated output results to the first fixed-address memory region, such that no data is spilled to disk;
transferring, by one or more computer processors, generated output results from the first fixed-address memory region to the reducer system using RDMA, wherein transferring includes performing an RDMA transfer of generated output results from the first fixed-address memory region to a second fixed-address memory region;
sorting, by one or more computer processors, the output results in the second fixed-address memory region; and
transferring, by one or more computer processors, the sorted output results from the second fixed-address memory region to a primary memory buffer, such that no data is spilled to disk.

2. The method of claim 1 , further comprising:
registering, by one or more computer processors, the second fixed-address memory region for the reducer system.

3. The method of claim 1 , wherein the RDMA transfer is performed using both InfiniBand and RDMA over Converged Ethernet (RoCE).

4. The method of claim 1 , further comprising:
transferring, by one or more computer processors, the generated output results from the second fixed-address memory region to a dynamic memory region; and
sorting, by one or more computer processors, the generated output results in the dynamic memory region.

5. A computer program product for transferring data in a MapReduce framework comprising a mapper system and a reducer system, the computer program product comprising:
one or more computer readable storage memory and program instructions stored on the one or more computer readable storage memory, the program instructions comprising:
program instructions to receive a data split assigned to a mapper system;
program instructions to register a first fixed-address memory region for the mapper system to be used for a remote direct memory access (RDMA) reducer buffer, wherein the first fixed-address memory region is a locked memory region, expressed as a fixed memory address followed by a specified byte range, that is separated from dynamic memory regions on a virtual machine used by the mapper system, and wherein registering includes determining a size for the RDMA reducer buffer to be created based on a size of an RDMA mapper buffer of the mapper system to which the reducer system is assigned, wherein the RDMA reducer buffer is sized such that no data is spilled to disk;
program instructions to execute one or more mapper tasks on the data split to generate output results;
program instructions to spill generated output results to the first fixed-address memory region, such that no data is spilled to disk;
program instructions to transfer generated output results from the first fixed-address memory region to the reducer system using RDMA, wherein transferring includes performing an RDMA transfer of generated output results from the first fixed-address memory region to a second fixed-address memory region;
sorting, by one or more computer processors, the output results in the second fixed-address memory region; and
transferring, by one or more computer processors, the sorted output results from the second fixed-address memory region to a primary memory buffer.

6. The computer program product of claim 5 , wherein the program instructions stored on the one or more computer readable storage memory further comprise:
program instructions to register a second fixed-address memory region for the reducer system.

7. The computer program product of claim 5 , wherein the RDMA transfer is performed using both InfiniBand and RDMA over Converged Ethernet (RoCE).

8. The computer program product of claim 5 , wherein the program instructions stored on the one or more computer readable storage memory further comprise:
program instructions to transfer the generated output results from the second fixed-address memory region to a dynamic memory region; and
program instructions to sort the generated output results in the dynamic memory region.

9. A computer system for transferring data in a MapReduce framework comprising a mapper system and a reducer system, the computer system comprising:
one or more computer processors;
one or more computer readable storage memory;
program instructions stored on the one or more computer readable storage memory for execution by at least one of the one or more processors, the program instructions comprising:
program instructions to receive a data split assigned to a mapper system;
program instructions to register a first fixed-address memory region for the mapper system to be used for a remote direct memory access (RDMA) reducer buffer, wherein the first fixed-address memory region is a locked memory region, expressed as a fixed memory address followed by a specified byte range, that is separated from dynamic memory regions on a virtual machine used by the mapper system, and wherein registering includes determining a size for the RDMA reducer buffer to be created based on a size of an RDMA mapper buffer of the mapper system to which the reducer system is assigned, wherein the RDMA reducer buffer is sized such that no data is spilled to disk;
program instructions to execute one or more mapper tasks on the data split to generate output results;
program instructions to spill generated output results to the first fixed-address memory region, such that no data is spilled to disk;
program instructions to transfer generated output results from the first fixed-address memory region to the reducer system using RDMA, wherein transferring includes performing an RDMA transfer of generated output results from the first fixed-address memory region to a second fixed-address memory region;
sorting, by one or more computer processors, the output results in the second fixed-address memory region; and
transferring, by one or more computer processors, the sorted output results from the second fixed-address memory region to a primary memory buffer.

10. The computer system of claim 9 , wherein the program instructions stored on the one or more computer readable storage memory further comprise:
program instructions to register a second fixed-address memory region for the reducer system.

11. The computer system of claim 9 , wherein the RDMA transfer is performed using both InfiniBand and RDMA over Converged Ethernet (RoCE).

12. The computer system of claim 9 , wherein the program instructions stored on the one or more computer readable storage memory further comprise:
program instructions to transfer the generated output results from the second fixed-address memory region to a dynamic memory re

Assignees

• IBM

Inventors

• Aslam Muhammad Sohaib
• Salo Tiia J

Classifications

• G06F9/5066 Primary

  Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs (mappping at compile time, see G06F8/451) · CPC title

• H04L12/06 Primary

  Answer-back mechanisms or circuits · CPC title