Method and apparatus for current/power balancing

Patent metadata

Field	Value
Publication number	US-9923560-B2
Application number	US-201615097853-A
Country	US
Kind code	B2
Filing date	Apr 13, 2016
Priority date	Apr 13, 2016
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

Aspects of the disclosure provide a system having a power circuit. The power circuit includes a first switch circuit having at least a first transistor and a second switch circuit having at least a second transistor. Further, the power circuit includes first interconnections configured to couple the first switch circuit to driving nodes, a source node and a drain node of the power circuit, and second interconnection configured to couple the second switch circuit in parallel to the first switch circuit to the driving nodes, the source node and the drain node of the power circuit. A polarity of unbalance in the first interconnections and the second interconnections dominates a polarity of current unbalance in the first switch circuit and the second switch circuit.

First claim

What is claimed is:

1. A power circuit, comprising:
a first switch circuit having at least a first transistor;
a second switch circuit having at least a second transistor;
first interconnections configured to couple the first switch circuit to driving nodes, a source node and a drain node of the power circuit; and
second interconnections configured to couple the second switch circuit parallel with the first switch circuit to the driving nodes, the source node and the drain node of the power circuit, wherein the first interconnections and the second interconnections are configured to be a dominant source for causing current/power unbalance among the first switch circuit and the second switch circuit such that a polarity of the current/power unbalance is consistent with configurations of the first and second interconnections in spite of other source including at least transistor parameter variations causing current/power unbalance.

2. The power circuit of claim 1 , wherein the first interconnections and the second interconnections are configured to be the dominant source for causing the current/power unbalance when a transistor parameter difference between the first transistor and the second transistor is within a range specified in manufacturing specifications.

3. The power circuit of claim 1 , wherein
a first interconnection is configured to couple a source terminal of the first transistor to the source node of the power circuit;
a second interconnection is configured to couple a source terminal of the second transistor to the source node of the power circuit; and
an unbalance between the first interconnection and the second interconnection is a dominant source for causing current/power unbalance among the first switch circuit and the second switch circuit.

4. The power circuit of claim 1 , further comprising:
a balancing circuit configured to balance current flowing through the first switch circuit and the second switch circuit based on the current/power unbalance among the first interconnections and the second interconnections.

5. The power circuit of claim 4 , wherein the balancing circuit is formed by mutually inductive-coupling of interconnections selected from the first interconnections and the second interconnections.

6. The power circuit of claim 1 , wherein the first transistor and the second transistor are SiC metal-oxide-semiconductor field effect transistors.

7. The power circuit of claim 1 , wherein the first switch circuit is on a first die, the second switch circuit is on a second die; and the first die and the second die are assembled in a package to form the power circuit.

8. A method for forming a power circuit, comprising:
disposing a first switch circuit and a second switch circuit;
coupling the first switch circuit to driving nodes, a source node and a drain node of the power circuit using first interconnections; and
coupling the second switch circuit in parallel with the first switch circuit to the driving nodes, the source node and the drain node of the power circuit using second interconnections that are unbalanced from the first interconnections, wherein the first interconnections and the second interconnections are configured to be a dominant source for causing current/power unbalance among the first switch circuit and the second switch circuit such that a polarity of the current/power unbalance is consistent with configurations of the first and second interconnections in spite of other source including at least transistor parameter variations causing current/power unbalance.

9. The method of claim 8 , further comprising:
receiving ranges of the transistor parameter variations in manufacturing specifications that are used to control transistor fabrication; and
determining, according to the range, the configuration of the first interconnections and the second interconnections to be the dominant source.

10. The method of claim 8 , wherein
coupling a source terminal of a first transistor in the first switch circuit to the source node of the power circuit using a first interconnection having a first inductance; and
coupling a source terminal of a second transistor in the second switch circuit to the source node of the power circuit using a second interconnection having a second inductance that is different from the first inductance, wherein a polarity of inductance unbalance between the first interconnection and the second interconnection is a dominant source for causing current/power unbalance among the first switch circuit and the second switch circuit.

11. The method of claim 8 , further comprising:
balancing current flowing through the first switch circuit and the second switch circuit based on the current/power unbalance among the first interconnections and the second interconnections.

12. The method of claim 11 , further comprising:
mutual-inductive coupling interconnections selected according to the polarity of unbalance in the first interconnections and the second interconnections.

13. A system having a power circuit, the power circuit comprising:
a first switch circuit having at least a first transistor;
a second switch circuit having at least a second transistor; and
first interconnections configured to couple the first switch circuit to driving nodes, a source node and a drain node of the power circuit; and
second interconnections configured to couple the second switch circuit in parallel with the first switch circuit to the driving nodes, the source node and the drain node of the power circuit, wherein the first interconnections and the second interconnections are configured to be a dominant source for causing current/power unbalance among the first switch circuit and the second switch circuit such that a polarity of the current/power unbalance is consistent with configurations of the first and second interconnections in spite of other source including at least transistor parameter variations causing current/power unbalance.

14. The system of claim 13 , wherein the first interconnections and the second interconnections are configured to be the dominant source for causing the current/power unbalance when a transistor parameter difference between the first transistor and the second transistor is within a range specified in manufacturing specifications.

15. The system of claim 13 , wherein
a first interconnection is configured to couple a source terminal of the first transistor to the source node of the power circuit;
a second interconnection is configured to couple a source terminal of the second transistor to the source node of the power circuit; and
an unbalance between the first interconnection and the second interconnection is a dominant source for causing current/power unbalance among the first switch circuit and the second switch circuit.

16. The system of claim 13 , further comprising:
a balancing circuit configured to balance current flowing through the first switch circuit and the second switch circuit according to the current/power unbalance among the first interconnections and the second interconnections.

17. The system of claim 16 , wherein the balancing circuit is formed by mutually inductive-coupling interconnections selected from the first interconnections and the second interconnections according to the unbalance in the first interconnections and the second interconnections.

18. The system of claim 13 , wherein the first transistor and the second transistor are SiC metal-oxide-semiconductor field effect transistors.

19. The system of claim 13 , wherein the fi

Assignees

• Toyota Eng & Mfg North America
• Virginia Tech Intellectual Properties Inc

Inventors

• Wang Chi-Ming
• MAO Yincan
• Miao Zichen
• Ngo Khai

Classifications

• G05F3/02 Primary

  Regulating voltage or current · CPC title

• H03K17/6871 Primary

  the output circuit comprising more than one controlled field-effect transistor · CPC title

• H03K17/0822

  in field-effect transistor switches · CPC title