Discrete time polyphase channelizer

Patent metadata

Field	Value
Publication number	US-9923549-B2
Application number	US-201514849524-A
Country	US
Kind code	B2
Filing date	Sep 9, 2015
Priority date	Sep 9, 2015
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

There is provided a finite impulse response (FIR) filter for filtering an input voltage signal to generate an output current signal, the FIR filter including a plurality of sample and hold (SH) circuits configured to simultaneously receive the input voltage signal, to sample the input voltage signal at successive sample times according to a sample clock, and to generate a plurality of sampled voltage signals, and a plurality of programmable analog multipliers coupled to the plurality of SH circuits and configured to multiply the plurality of sampled voltage signals by a plurality of binary multiplication factors to generate the output current signal.

First claim

What is claimed is:

1. A finite impulse response (FIR) filter for filtering an input voltage signal to generate an output current signal, the FIR filter comprising:
a plurality of sample and hold (SH) circuits configured to simultaneously receive the input voltage signal, to sample the input voltage signal at successive sample times according to a sample clock, and to generate a plurality of sampled voltage signals;
a plurality of programmable analog multipliers coupled to the plurality of SH circuits and configured to multiply the plurality of sampled voltage signals by a plurality of binary multiplication factors to generate the output current signal, each of the programmable analog multipliers being a voltage-to-current multiplier;
a power controller configured to dynamically adjust a filtering profile of the FIR filter by selectively and dynamically activating or deactivating ones of the plurality of programmable analog multipliers during operation of the FIR filter; and
a plurality of rotating shift registers configured to circularly rotate the plurality of binary multiplication factors through memory positions of the plurality of rotating shift registers at each one of the successive sample times, and to supply the plurality of binary multiplication factors to the plurality of programmable analog multipliers,
wherein, in response to the power controller selectively and dynamically activating or deactivating ones of the plurality of programmable analog multipliers, the plurality of rotating shift registers are configured to correspondingly adjust a number of the memory positions and a number of the plurality of binary multiplication factors,
wherein outputs of odd ones of the plurality of programmable analog multipliers are electrically shorted together and outputs of even ones of the plurality of programmable analog multipliers are electrically shorted together to respectively generate an odd output current signal and an even output current signal, and
wherein the output current signal comprises the odd and even output current signals.

2. The FIR filter of claim 1 , wherein the plurality of sampled voltage signals have a same duration and are staggered in time.

3. The FIR filter of claim 1 , further comprising a timing controller configured to generate a plurality of control signals for triggering sample times of the plurality of SH circuits, wherein consecutive ones of the plurality of control signals are offset in time by a sampling period.

4. The FIR filter of claim 1 , wherein each one of the plurality of programmable analog multipliers is configured to convert a respective one of the plurality of sampled voltage signals to a current signal before multiplying the current signal by a respective one of the plurality of binary multiplication factors.

5. The FIR filter of claim 1 , wherein each one of the plurality of rotating shift registers comprises a localized calibration value associated with a respective one of the plurality of programmable analog multipliers, the localized calibration value compensating for gain errors of the respective one of the plurality of programmable analog multipliers.

6. The FIR filter of claim 1 , wherein a frequency of the sample clock is programmable.

7. A programmable discrete time analog channelizer configured to selectively filter an analog input signal, the programmable discrete time analog channelizer comprising:
a plurality of FIR filters, each of the plurality of FIR filters configured to receive a sample stream of a plurality of sample streams and comprising:
a plurality of sample and hold (SH) circuits configured to simultaneously receive the sample stream, to sample the sample stream at successive sample times, and to generate a plurality of sampled voltage signals;
a plurality of programmable analog multipliers coupled to the plurality of SH circuits and configured to multiply the plurality of sampled voltage signals by a plurality of binary multiplication factors to generate an output current signal of a plurality of output current signals, each of the programmable analog multipliers being a voltage-to-current multiplier;
a power controller configured to dynamically adjust a filtering profile of the FIR filter by selectively and dynamically activating or deactivating ones of the plurality of programmable analog multipliers during operation of the FIR filter; and
a plurality of rotating shift registers configured to circularly rotate the plurality of binary multiplication factors through memory positions of the plurality of rotating shift registers at each one of the successive sample times, and to supply the plurality of binary multiplication factors to the plurality of programmable analog multipliers,
wherein, in response to the power controller selectively and dynamically activating or deactivating ones of the plurality of programmable analog multipliers, the plurality of rotating shift registers are configured to correspondingly adjust a number of the memory positions and a number of the plurality of binary multiplication factors,
wherein outputs of odd ones of the plurality of programmable analog multipliers are electrically shorted together and outputs of even ones of the plurality of programmable analog multipliers are electrically shorted together to respectively generate an odd output current signal and an even output current signal, and wherein the output current signal comprises the odd and even output current signals; and

a plurality of fourier transform circuits configured to multiply the plurality of output current signals by a plurality of fourier transform coefficients to generate a plurality of fourier transform outputs, a summation of the plurality of fourier transform outputs comprising a filtered output of the programmable discrete time analog channelizer,
wherein the plurality of sample streams represents the analog input signal.

8. The programmable discrete time analog channelizer of claim 7 , wherein the plurality of binary multiplication factors are programmable and determine a profile of the filtered output.

9. The programmable discrete time analog channelizer of claim 7 , wherein the plurality of fourier transform coefficients are programmable and determine a center frequency of the filtered output.

10. The programmable discrete time analog channelizer of claim 7 , further comprising a timing controller configured to generate a plurality of enable signals for triggering sample times of the plurality of SH circuits of the plurality of FIR filters, wherein consecutive ones of the plurality of enable signals are offset in time by a sampling period.

11. The programmable discrete time analog channelizer of claim 7 , further comprising a polyphase sampler configured to receive the analog input signal and to downsample the analog input signal, and to generate the plurality of sample streams.

12. The programmable discrete time analog channelizer of claim 7 , further comprising an accumulator configured to sum the plurality of fourier transform outputs and to convert the summed plurality of fourier transform outputs to a voltage signal.

13. A programmable discrete time analog upsampler configured to generate a radio frequency (RF) voltage signal based on a baseband input signal, the programmable discrete time analog upsampler comprising:
a plurality of sample and hold (SH) circuits configured to simultaneously receive the baseband input signal, to sample the baseband input signal at successive sample times, and to generate a plurality of sampled voltage signals;
a plurality of programmable analog multipliers coupled to the plurality of SH circuits and configured to multiply the plural

Assignees

• Raytheon Co

Inventors

• Kultran Denpol
• Hennegan Richard T
• Marr Harry B

Classifications

• H03H19/00

  Networks using time-varying elements, e.g. N-path filters · CPC title

• H03H15/00 Primary

  Transversal filters (electromechanical filters H03H9/46, H03H9/70) · CPC title