Semiconductor structure with inhomogeneous regions

US9923118B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9923118-B2
Application numberUS-201615225403-A
CountryUS
Kind codeB2
Filing dateAug 1, 2016
Priority dateFeb 25, 2013
Publication dateMar 20, 2018
Grant dateMar 20, 2018

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A semiconductor layer including a plurality of inhomogeneous regions is provided. Each inhomogeneous region has one or more attributes that differ from a material forming the semiconductor layer. The inhomogeneous regions can include one or more regions configured based on radiation having a target wavelength. These regions can include transparent and/or reflective regions. The inhomogeneous regions also can include one or more regions having a higher conductivity than a conductivity of the radiation-based regions, e.g., at least ten percent higher. In one embodiment, the semiconductor layer is used to form an optoelectronic device.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor heterostructure, comprising: an active region configured to at least one of: emit or sense, target radiation having a target wavelength; a contact; and a group III nitride semiconductor layer located between the active region and the contact, the group III semiconductor layer including a plurality of inhomogeneous regions arranged within multiple levels of the semiconductor layer, each having a set of attributes differing from a group III nitride material forming the group III semiconductor layer, wherein the plurality of inhomogeneous regions include at least one reflective region and at least one conductive region. 2. The semiconductor heterostructure of claim 1 , wherein the at least one reflective region comprises a set of low refractive index sublayers alternating with a set of highly reflective sublayers. 3. The semiconductor heterostructure of claim 2 , wherein a thickness of each sublayer in the at least one reflective region is approximately a quarter of the target wavelength. 4. The semiconductor heterostructure of claim 2 , wherein at least one of the set of low refractive index sublayers includes a set of conductive sub-regions forming a set of passages through the at least one of the set of low refractive index sublayers. 5. The semiconductor heterostructure of claim 2 , wherein the set of low refractive index sublayers include a material selected from: silicon dioxide, aluminum oxide, or a group III nitride. 6. The semiconductor heterostructure of claim 2 , wherein each sublayer in the at least one reflective region is formed of a group III nitride composition. 7. The semiconductor heterostructure of claim 1 , wherein the at least one reflective region forms an omnidirectional mirror. 8. The semiconductor heterostructure of claim 1 , wherein at least one of the at least one reflective region penetrates the contact. 9. The semiconductor heterostructure of claim 1 , wherein the contact is a p-type contact. 10. A method, comprising: fabricating a semiconductor heterostructure, wherein the semiconductor heterostructure comprises: an active region configured to at least one of: emit or sense, target radiation having a target wavelength; and a single group III nitride semiconductor layer located adjacent to the active region, the group III semiconductor layer including a plurality of inhomogeneous regions arranged within multiple levels of the semiconductor layer, each having a set of attributes differing from a group III nitride material forming the group III semiconductor layer, wherein the plurality of inhomogeneous regions include at least one reflective region and at least one conductive region. 11. The method of claim 10 , further comprising forming a contact immediately adjacent to the group III nitride semiconductor layer. 12. The method of claim 10 , wherein the fabricating includes: epitaxially growing a portion of the group III nitride semiconductor layer; forming at least one of the sets of inhomogeneous regions on a surface of the portion of the group III nitride semiconductor layer; and epitaxially over-growing the group III nitride semiconductor layer after the forming. 13. The method of claim 12 , wherein the forming includes: depositing the at least one of the sets of inhomogeneous regions using one of: thermal evaporation, magnetron sputtering, ion-beam deposition, or laser beam evaporation; and patterning the at least one of the sets of inhomogeneous regions using photolithography. 14. An optoelectronic device, comprising: an active region configured to at least one of: emit or sense, target radiation having a target wavelength; a p-type contact layer located on a first side of the active region; a n-type contact layer located on a second side of the active region, the n-type contact layer including a group III nitride semiconductor layer including a plurality of inhomogeneous regions, each inhomogeneous region having a set of attributes differing from a group III nitride material forming the group III semiconductor layer, wherein the plurality of inhomogeneous regions include a plurality of reflective regions each reflective of radiation having the target wavelength; a buffer layer located on a first side of the n-type contact layer opposite a second side thereof that is located adjacent to the active region; and a transparent substrate, located on a first side of the buffer layer opposite a second side thereof that is located adjacent to the n-type contact layer, wherein the transparent substrate is at least 80% transparent to a normally directed target radiation. 15. The optoelectronic device of claim 14 , wherein the transparent substrate comprises a plurality of roughness elements on a first side of the transparent substrate opposite a second side thereof that is located adjacent to the buffer layer. 16. The optoelectronic device of claim 15 , wherein each of the roughness elements has a characteristic size that is at least the characteristic size of the target wavelength of the target radiation. 17. The optoelectronic device of claim 15 , wherein the second side of the transparent substrate comprises a plurality of masking regions. 18. The optoelectronic device of claim 17 , wherein the plurality of masking regions comprise one of reflective elements and scattering elements. 19. The optoelectronic device of claim 14 , further comprising a p-type metal layer formed over the p-type contact layer and a n-type metal layer formed over the n-type contact layer. 20. The optoelectronic device of claim 19 , further comprising a plurality of scattering elements located in each of the p-type metal layer and the n-type metal layer.

Assignees

Inventors

Classifications

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9923118B2 cover?
A semiconductor layer including a plurality of inhomogeneous regions is provided. Each inhomogeneous region has one or more attributes that differ from a material forming the semiconductor layer. The inhomogeneous regions can include one or more regions configured based on radiation having a target wavelength. These regions can include transparent and/or reflective regions. The inhomogeneous re…
Who is the assignee on this patent?
Sensor Electronic Tech Inc
What technology area does this patent fall under?
Primary CPC classification H01L33/10. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 20 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).